System and method of merging partial write results for resolving renaming size issues
AssigneeShanghai Zhaoxin Semiconductor Co., Ltd.
InventorsXiaolong Fei, Mengchen Yang
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Abstract
A processor including a physical register file with multiple physical registers, mapping logic, and a merge system. The mapping logic maps up to a first maximum number of the physical registers for each architectural register specified in received program instructions and stores corresponding mappings in a rename table. The merge system generates a merge instruction for each architectural register that needs to be merged, inserts each generated merge instruction into the program instructions to provide a modified set of instructions, and that issues the modified set of instructions in consecutive issue cycles based on a take rule. In one embodiment, the first maximum number may be two.
Claims20
A processor, comprising:
- a physical register file comprising a plurality of physical registers;
- mapping logic that maps up to a first maximum number of said plurality of physical registers for each of a plurality of architectural registers specified in a plurality of program instructions and that stores corresponding mappings in a rename table;
- and
- a merge system that generates only a single merge instruction for each of said plurality of architectural registers that is mapped to by multiple physical registers in which partial results are stored and thus needs to be merged, the merge system also inserts a plurality of merge instructions into said plurality of program instructions to provide a modified set of instructions, wherein the merge system determines which of said plurality of merge instructions should be inserted before any of said plurality of program instructions, and that issues said modified set of instructions in consecutive issue cycles based on a take rule.
A method of merging partial write results for resolving renaming size issues for a processor, comprising:
- mapping each of a plurality of architectural registers specified in a plurality of program instructions in a rename table into up to a first maximum number of a plurality of physical registers;
- detecting when any of said plurality of architectural registers needs to be merged before execution of at least one of the plurality of program instructions;
- generating only a single merge instruction for each of said plurality of architectural registers that is mapped to by multiple physical registers in which partial results are stored and thus needs to be merged;
- inserting a plurality of merge instructions into the plurality of program instructions to provide a modified set of instructions, wherein which of said plurality of merge instructions should be inserted before any of said plurality of program instructions is determined;
- and
- issuing the modified set of instructions in consecutive clock cycles based on a take rule.
A processor, comprising:
- a physical register file comprising a plurality of physical registers;
- mapping logic that maps up to a first maximum number of said plurality of physical registers for each of a plurality of architectural registers specified in a plurality of program instructions and that stores corresponding mappings in a rename table;
- and
- a merge system that generates only a single merge instruction for each of said plurality of architectural registers that is mapped to by multiple physical registers in which partial results are stored and thus needs to be merged, the merge system also inserts a plurality of merge instructions into said plurality of program instructions to provide a modified set of instructions, wherein the plurality of merge instructions are generated for said plurality of program instructions, and that issues said modified set of instructions in consecutive issue cycles based on a take rule.
Dependencies are inferred from the claim text.