Method and apparatus for supporting speculative memory optimizations
AssigneeIntel Corporation
InventorsVineeth Mekkat, Mark Dechene, Zhongying Zhang, John Faistl, Janghaeng Lee, Hou-Jen Ko, Sebastian Winkel, Oleg Margulis
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Abstract
A processor includes a store buffer to store store instructions to be processed to store data in main memory, a load buffer to store load instructions to be processed to load data from main memory, and a loop invariant code motion (LICM) protection structure coupled to the store buffer and the load buffer. The LPT tracks information to compare an address of a store or snoop microoperation with entries in the LICM and re-loads a load microoperation of a matching entry.
Claims20
A processor comprising:
- a store buffer to store store instructions to be processed to store data in main memory;
- a load buffer to store load instructions to be processed to load data from main memory;
- a loop invariant code motion (LICM) protection structure coupled to the store buffer and the load buffer, the LICM protection structure to track information to compare an address of a store or snoop microoperation with entries in the LICM protection structure;
- and
- an address generation unit (AGU) coupled to the LICM protection structure, the AGU to check whether a store or snoop operation is in a read modify write (RMW) sequence, the AGU to bypass the LICM protection structure for a matching entry in a check of the LICM protection structure for a detected RMW sequence.
A computer system comprising:
- a main memory;
- and
- a system on a chip coupled to the main memory, the system on a chip including a processor including a pipeline with a store buffer to store store instructions to be processed to store data in main memory, a load buffer to store load instructions to be processed to load data from main memory, a loop invariant code motion (LICM) protection structure coupled to the store buffer and the load buffer, the LICM protection structure to track information to compare an address of a store or snoop microoperation with entries in the LICM an address generation unit (AGU) coupled to the LICM protection structure the AGU to check whether a store or snoop operation is in a read modify write (RMW) sequence, the AGU to bypass the LICM protection structure for a for a matching entry in a check of the LICM protection structure for a detected RMW sequence.
A non-transitory computer readable medium having stored therein a set of instructions, which when executed cause a computer to perform a set of operations comprising:
- storing store instructions in a store buffer to be processed to store data in main memory;
- storing load instructions in a load buffer to be processed to load data from main memory;
- identifying a loop invariant code motion (LICM) in a code sequence;
- updating a LICM protection structure to track information about the LICM in the code sequence;
- comparing an address of a store or snoop microoperation with entries in the LICM;
- and
- checking whether the store or snoop operation is in a read modify write (RMW) sequence to bypass the LICM protection structure for detected RMW sequences.
Dependencies are inferred from the claim text.