Table fetch processor instruction using table number to base address translation

A processor comprising:

• means for fetching blocks of information from a memory system external to the processor without the use of an instruction counter, wherein the means only fetches blocks of information from the memory system in response to either a receiving of a fetch information value onto the processor from an external source or to a receiving of a fetch information value from a stage within the processor, wherein the processor includes no instruction counter and the means fetches a block of information without use of any instruction counter, wherein a fetch information value received onto the processor from the external source includes a table number value, wherein the means determines a base address value from the table number value, and wherein the base address value is supplied as part of a memory request that is supplied from the means to the memory system, and wherein the base address value is a base address of a table that contains the block of information;
• a decode stage coupled to the means, wherein the decode stage can decode a fetch instruction, wherein the fetch instruction includes an opcode indicating that the fetch instruction is a fetch instruction, wherein execution by the processor of a fetch instruction involves decoding of the opcode of the fetch instruction;
• a register file read stage coupled to the decode stage;
• and
• an execute stage coupled to the register file read stage, wherein the execute stage executes the fetch instruction by outputting fetch information to the means thereby prompting the means to fetch a block of information.

A system comprising:

• a processor comprising:
• means for fetching blocks of information without the use of an instruction counter, wherein the means only fetches blocks of information in response to either a receiving of a fetch information value onto the processor from an external source or to a receiving of a fetch information value from a stage within the processor, wherein the processor includes no instruction counter and the means fetches blocks of information without use of any instruction counter, wherein a fetch information value received onto the processor from the external source includes a table number value;
• a decode stage coupled to the means, wherein the decode stage can decode a fetch instruction, wherein the fetch instruction includes an opcode indicating that the fetch instruction is a fetch instruction, wherein execution by the processor of a fetch instruction involves decoding of the opcode of the fetch instruction;
• a register file read stage coupled to the decode stage;
• and
• an execute stage coupled to the register file read stage, wherein the execute stage executes the fetch instruction by outputting fetch information to the means thereby prompting the means to fetch a block of information;
• and
• a memory system external to the processor, wherein the memory system receives a memory request from the processor, wherein the memory request includes the table number value, wherein the memory system determines a base address value from the table number value, and wherein the base address value is a base address of a table of code stored in the memory system that contains the block of information.

A method comprising:

• (a) receiving an initial fetch information value onto a processor, wherein the processor does not include any instruction counter, and wherein the initial fetch information value is a multi-bit value that is received in (a) onto a port of the processor;
• (b) using the initial fetch information value to determine a base address value and an offset value, wherein the base address value is a base address of a table of code in an external memory, and wherein the offset value indicates an offset from the base address to a section of code within the table;
• (c) in response to the receiving of the initial fetch information value of (a) fetching a first block of information of the section of code without use by the processor of any instruction counter, wherein the first block of information includes a plurality of instructions, wherein at least one of the instructions of the first block is a fetch instruction, wherein the fetch instruction includes an opcode indicating that the fetch instruction is a fetch instruction, wherein execution by the processor of a fetch instruction involves decoding of the opcode of the fetch instruction, and wherein the processor only fetches instructions in response to receiving an initial fetch information value from an external source onto the port or as a result of executing a fetch instruction;
• and
• (d) executing the instructions of the first block of information including executing the fetch instruction, and wherein (a), (b), (c) and (d) are performed by the processor.

A method comprising:

• (a) generating a set of flags from a network packet, wherein the set of flags characterizes the network packet;
• (b) receiving prompting information onto a processor, wherein the set of flags is a part of the prompting information, wherein the processor does not include any instruction counter, and wherein the processor is not clocking when the prompting information is received in (b);
• (c) using the set of flags to determine an address of a block of information in a memory external to the processor, wherein the block of information includes a plurality of instructions executable by the processor, wherein at least one of the instructions is a fetch instruction, wherein the fetch instruction includes an opcode indicating that the fetch instruction is a fetch instruction, wherein execution by the processor of a fetch instruction involves decoding of the opcode of the fetch instruction, and wherein the processor only fetches instructions in response to receiving prompting information onto the processor or as a result of executing a fetch instruction;
• (d) in response to the receiving of the prompting information in (b) causing the processor to start clocking;
• (e) in response to the receiving of the prompting information in (b) fetching the block of information from the memory without use by the processor of any instruction counter;
• and
• (f) executing the instructions of the block of information including executing the fetch instruction, and wherein (b), (c), (d), (e) and (f) are performed by the processor.