Arithmetic processing apparatus and method of controlling arithmetic processing apparatus

An arithmetic processing apparatus, comprising:

• an instruction controller configured to issue an instruction;
• a first level cache including
• a translation lookaside buffer for storing part of a translation table entry in a memory,
• a first level data cache memory for storing part of data in the memory, and
• a first level cache controller configured to perform hit determination for the translation lookaside buffer in response to a memory access instruction issued by the instruction controller, and configured to perform cache control for the first level data cache memory when the hit determination for the translation lookaside buffer results in a hit;
• and
• a second level cache including
• a second level cache memory for storing part of data in the memory, and
• a second level cache controller configured to control a data request in response to a data request issued by the first level cache controller, wherein
• the instruction controller, when the memory access instruction is a memory access instruction to be speculatively executed that is executed while a branch destination of a branch instruction is undetermined, adds a valid speculation flag and an instruction identifier of the branch instruction to the memory access instruction and issues the memory access instruction to the first level cache, and
• when in a first case in which in the hit determination for the translation lookaside buffer, a virtual address of the issued memory access instruction matches a virtual address of any of entries in the translation lookaside buffer is satisfied, and when in a second case in which the speculation flag of the issued memory access instruction is valid and an entry having a virtual address matching the virtual address of the memory access instruction stores a speculative access prohibition flag prohibiting speculative access is satisfied, the first level cache controller interrupts execution of the issued memory access instruction, and
• when the first case is satisfied and the second case is not satisfied, the cache control is performed for the first level data cache memory by using a physical address read from the translation lookaside buffer.