Processor suspension buffer and instruction queue

A processor, comprising:

• a vector processing engine;
• and
• a scalar processor, which is configured to:
• fetch, from a memory, Very Long Instruction Word (VLIW) instructions that comprise both scalar-instruction slots and vector-instruction slots;
• extract scalar instructions from the scalar-instruction slots of the VLIW instructions, and execute the scalar instructions;
• and
• extract, from the vector-instruction slots of the VLIW instructions, vector instructions comprising read instructions for reading data from the memory;
• pre-process the vector instructions, including:
• requesting the data from the memory in a first order;
• receiving the data from the memory into a data buffer in a second order that is different from the first order, but providing the data to the vector processing engine, using the data buffer, in the first order;
• and
• transfer the pre-processed vector instructions to the vector processing engine for execution.

A processor, comprising:

• a vector processing engine;
• and
• a scalar processor, which is configured to:
• fetch, from a memory, Very Long Instruction Word (VLIW) instructions that comprise both scalar-instruction slots and vector-instruction slots;
• extract scalar instructions from the scalar-instruction slots of the VLIW instructions, and execute the scalar instructions;
• extract vector instructions from the vector-instruction slots of the VLIW instructions, pre-process the vector instructions, and transfer the pre-processed vector instructions to the vector processing engine for execution;
• and
• two or more counters that are allocated to respective kernels processed by the vector processing engine, wherein each counter is configured to count write operations to the memory that were requested by the scalar processor but not yet completed, and wherein, when one of the counters is decremented to zero, the scalar processor is configured to indicate to the vector processing engine that data for the corresponding kernel is ready in the memory.

A method in a processor that comprises a scalar processor and a vector processing engine, the method comprising:

• using the scalar processor:
• fetching from a memory Very Long Instruction Word (VLIW) instructions that comprise both scalar-instruction slots and vector-instruction slots;
• extracting scalar instructions from the scalar-instruction slots of the VLIW instructions, and executing the scalar instructions;
• extracting, from the vector-instruction slots of the VLIW instructions, vector instructions comprising read and write instructions that access data in the memory;
• pre-processing the vector instructions,
• including:
• generating addresses for use by the vector processing engine in accessing the data;
• storing the generated addresses in an address queue;
• and
• accessing the memory on behalf of the vector processing engine while compensating for variations in access latency to the memory, by reading the addresses from the address queue and executing the vector instructions in the memory in accordance with the addresses read from the address queue;
• and
• transferring the pre-processed vector instructions to the vector processing engine;
• and executing the pre-processed vector instructions using the vector processing engine.

A method in a processor that comprises a scalar processor and a vector processing engine, the method comprising:

• using the scalar processor:
• fetching from a memory Very Long Instruction Word (VLIW) instructions that comprise both scalar-instruction slots and vector-instruction slots;
• extracting scalar instructions from the scalar-instruction slots of the VLIW instructions, and executing the scalar instructions;
• and
• extracting, from the vector-instruction slots of the VLIW instructions, vector instructions comprising read instructions for reading data from the memory;
• pre-processing the vector instructions,
• including:
• requesting the data from the memory in a first order;
• receiving the data from the memory into a data buffer in a second order that is different from the first order, but providing the data to the vector processing engine, using the data buffer, in the first order;
• and
• transferring the pre-processed vector instructions to the vector processing engine;
• and
• executing the pre-processed vector instructions using the vector processing engine.

A method in a processor that comprises a scalar processor and a vector processing engine, the method comprising:

• using the scalar processor:
• fetching from a memory Very Long Instruction Word (VLIW) instructions that comprise both scalar-instruction slots and vector-instruction slots;
• extracting scalar instructions from the scalar-instruction slots of the VLIW instructions, and executing the scalar instructions;
• and
• extracting vector instructions from the vector-instruction slots of the VLIW instructions, pre-processing the vector instructions and transferring the pre-processed vector instructions to the vector processing engine;
• executing the pre-processed vector instructions using the vector processing engine;
• and
• allocating two or more counters to respective kernels processed by the vector processing engine, counting in each counter write operations to the memory that were requested by the scalar processor but not yet completed, and, when one of the counters is decremented to zero, indicating by the scalar processor to the vector processing engine that data for the corresponding kernel is ready in the memory.