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US 10,853,066 B1Granted
Memory processing units and methods of computing DOT products including zero bit skipping
AssigneeMemryX Incorporated
InventorsChester Liu, Mohammed Zidan, Wei Lu, Zhengya Zhang
Life of this patent
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Abstract
A memory processing unit can be configured to compute partial products between one or more elements of a first matrix stored in a first storage location and sequential bits of one or more elements of a second matrix stored in a second storage location. The partial products can be calculated utilizing zero bit skipping to increase throughput and or reduce energy consumption. The partial products for each column of elements can be accumulated and bit shifted to compute the dot product of the first and second matrix.
Claims17
A device comprising:
- a first storage location configured to store a set of multipliers;
- a second storage location configured to store a set of multiplicands;
- a bit skipping logic configured to determine rows for a given bit position in the second storage location that hold non-zero values;
- one or more readout circuitry configured to;
- sequential bias rows of the first storage location corresponding to non-zero value rows for the given bit position in the second storage location;
- and
- sequentially sense the rows of the first storage location, corresponding to the rows for the given bit position in the second storage location containing non-zero values, to determine partial products for the given bit position;
- one or more accumulators configured to accumulate the determined partial products for the given bit position;
- and
- one or more shift registers configured to shift the accumulated values, after sequentially accumulating the determined partial products for the plurality of bit positions over the plurality of rows of the first storage location, as a matrix dot product of the set of multipliers and the set of multiplicands.
7 more elements
A device comprising:
- a first storage location configured to store a set of multipliers;
- a second storage location configured to store a set of multiplicands;
- a bit masking logic configured to;
- sequentially access respective rows of the second storage location to determine if a given bit position of the given row in the second storage location is a non-zero value;
- and
- conditionally sequentially accessing rows of the first storage location corresponding to given rows in the second storage location when a given bit position of the given row in the second storage location is a non-zero value;
- logic AND circuitry configured to conditionally bitwise AND the given bit position of the given row of the second storage location and the given row of the first storage location, when the given bit position of the given row in the second storage location is a non-zero value to generate partial products for the given bit position;
- one or more accumulators configured to conditionally accumulate the partial products for the given bit position when the bit position of the given row in the second storage location is a non-zero value;
- one or more shift registers configured to shift the accumulated value in a corresponding direction, wherein the given bit position in the second storage location is sequentially shifted in a predetermined direction.
6 more elements
Dependencies are inferred from the claim text.