Systems, apparatuses, and methods for chained fused multiply add

A method comprising:

• hardware decoding a single instruction having an opcode, a destination field representing a destination operand, a first source field representing a plurality of vector source operands of a first type that have data elements of a first size, a second source field representing a plurality of vector source operands that have data elements of a second size, and a field for a location that stores a scalar value;
• and
• executing the decoded single instruction with execution circuitry according to the opcode to perform iterations of fused multiply accumulate operations by multiplying data elements of the sources of the first type by sub-elements of the scalar value, and adding results of these multiplications to an initial value in a first iteration and a result from a previous iteration in subsequent iterations.

A non-transitory machine-readable medium storing an instruction which when processed by a processor causes the processor to perform a method, the method comprising:

• hardware decoding the instruction having an opcode, a destination field representing a destination operand, a first source field representing a plurality of vector source operands of a first type that have data elements of a first size, a second source field representing a plurality of vector source operands that have data elements of a second size, and a field for a location that stores a scalar value;
• and
• executing the decoded single instruction according to the opcode with execution circuitry to perform iterations of fused multiply accumulate operations by multiplying data elements of the sources of the first type by sub-scalar value, and adding results of these multiplications to an initial value in a first iteration and a result from a previous iteration in subsequent iterations.