Digital circuit with compressed carry
AssigneeGroq, Inc.
InventorsChristopher Aaron Clark, Jonathan Ross
Life of this patent
Estimating the term…
Abstract
Embodiments of the present disclosure pertain to digital circuits with compressed carries. In one embodiment, an adder circuit generates a sum and carry. The carry is compressed to reduce the number of bits required to represent the carry. In one embodiment, a multiplier circuit generates output product values. The output product values may be summed to produce a sum and carry. The carry may be compressed. In other embodiments, a multiplier circuit receives an input sum and compressed carry. The compressed input carry is decompressed and added to output product values and the input sum, and a resulting carry is compressed. The output of such a multiplier is another sum and compressed carry.
Claims20
A digital circuit comprising:
- a first multiplier circuit configured to produce an output product value by multiplying a first operand and a second operand;
- at least one adder circuit configured to add the output product value to at least one other value to produce a first sum and a first carry;
- and
- a compression circuit configured to add each segment of the first sum to a corresponding segment of the first carry producing each segment of a final sum and each bit of a compressed carry.
A method comprising:
- multiplying, in a first multiplier circuit, a first operand and a second operand to produce an output product value;
- adding, in at least one adder circuit, the output product value to at least one other value to produce a first sum and a first carry;
- and
- adding each segment of the first sum to a corresponding segment of the first carry to produce each segment of a final sum and each bit of a compressed carry.
A non-transitory machine-readable medium storing a hardware description language program, the hardware description language program comprising sets of instructions, which when executed produce a digital circuit comprising:
- a first multiplier circuit configured to produce an output product value by multiplying a first operand and a second operand;
- at least one adder circuit configured to add the at least one output product value to at least one other value to produce a first sum and a first carry;
- and
- a compression circuit configured to add each segment of the first sum to a corresponding segment of the first carry producing each segment of a final sum and each bit of a compressed carry.
Dependencies are inferred from the claim text.