Modulo hardware generator
AssigneeImagination Technologies Limited
InventorSamuel Lee
Life of this patent
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Abstract
A method of generating a hardware design to calculate a modulo value for any input value in a target input range with respect to a constant value d using one or more range reduction stages. The hardware design is generated through an iterative process that selects the optimum component for mapping successively increasing input ranges to the target output range until a component is selected that maps the target input range to the target output range. Each iteration includes generating hardware design components for mapping the input range to the target output range using each of a plurality of modulo preserving range reduction methods, synthesizing the generated hardware design components, and selecting one of the generated hardware design components based on the results of the synthesis.
Claims20
A computer-implemented method of generating a hardware design to calculate a modulo value for any integer input value in a target input range with respect to a constant value d, the hardware design comprising one or more range reduction stages, the method comprising in a processing module:
- (a) generating at least one hardware design component to map a desired input range to a target output range using each of a plurality of modulo preserving range reduction methods;
- (b) selecting one of the hardware design components as a preferred hardware design component for the desired input range;
- and
- (c) expanding the desired input range and repeating (a) to (c) until an input range of the preferred hardware design component comprises the target input range.
A modulo hardware generation engine to generate a hardware design to calculate a modulo value for any integer input value in a target input range with respect to a constant value d, the hardware design comprising one or more range reduction stages, the engine comprising:
- a plurality of range reduction modules, each range reduction module configured to generate a hardware design component to map an input range using one of a plurality of modulo preserving range reduction methods;
- decision logic in communication with the plurality of range reduction modules, the decision logic configured to:
- (a) generate at least one hardware design component to map a desired input range to a target output range using each of the plurality of range reduction modules;
- (b) select one of the hardware design components as preferred hardware design component for the desired input range;
- and
- (c) expand the desired input range and repeat (a) to (c) until an input range of the preferred hardware design component comprises the target input range.
A non-transitory computer readable storage medium having stored thereon computer readable code configured to generate a hardware design to calculate a modulo value for any integer input value in a target input range with respect to a constant value d, the hardware design comprising one or more range reduction stages, the code comprising code for:
- (a) generating at least one hardware design component to map a desired input range to a target output range using each of a plurality of modulo preserving range reduction methods;
- (b) selecting one of the hardware design components as a preferred hardware design component for the desired input range;
- and
- (c) expanding the desired input range and repeating (a) to (c) until an input range of the preferred hardware design component comprises the target input range.
Dependencies are inferred from the claim text.