Common factor mass multiplication circuitry

A circuit, comprising:

• common factor mass multiplication (CFMM) circuitry that multiplies a common factor by a plurality of multiplier values to generate a plurality of final products, the CFMM circuitry comprising:
• a common factor mass multiplication (CFMM) predetermined fixed constants multiplier circuit that multiplies the common factor by predetermined fixed constants to generate corresponding common partial products, wherein the predetermined fixed constants represent a minimized set of constants for generating all binary values of the common partial products with up to j logic ones by only shifting the minimized set of constants left or right such that the common partial products is generated using a reduced number of add or subtract operations, wherein j is any integer greater than one, wherein the predetermined fixed constants also include a value with all ones, wherein the predetermined fixed constants are independent of the value of the common factor and the plurality of multiplier values, and wherein the generation of the common partial products is amortized across the generation of the plurality of final products;
• a selection and shifting circuit that receives the common partial products from the CFMM predetermined fixed constants multiplier circuit and that is controlled by the plurality of multiplier values;
• and
• an arithmetic circuit that receives signals from the selection and shifting circuit and that is controlled by the plurality of multiplier values to compute the plurality of final products, wherein at least one of (1) the arithmetic circuit and (2) the reduced number of add or subtraction operations is implemented using bit-serial adder circuits.