Memory systems having semiconductor memory modules therein that support page fault processing
AssigneeSamsung Electronics Co., Ltd.
InventorsYongjun Yu, Insu Choi, Dae-Jeong Kim, Sung-Joon Kim, Wonjae Shin
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Abstract
Memory systems include a first semiconductor memory module and a processor. The processor is configured to access the first semiconductor memory module by units of a page, and further configured to respond to an occurrence of a page fault in a specific page, which is associated with a virtual address corresponding to an access target, by adjusting a number of pages and allocating pages in the first semiconductor memory module corresponding to the adjusted number of the pages, which are associated with the virtual address.
Claims15
A memory system, comprising:
- a first semiconductor memory module;
- and
- a processor configured to:
- (i) access the first semiconductor memory module by units of a page;
- and (ii) respond to an occurrence of a page fault in a specific page, which is associated with a virtual address corresponding to an access target, by adjusting a number of pages and allocating pages in the first semiconductor memory module corresponding to the adjusted number of the pages, which are associated with the virtual address, said adjusting comprising adjusting the number of pages to a number of previously allocated pages associated with a prior access to the first semiconductor memory module when a virtual address of the prior access and the virtual address of the access are successive and the number of the allocated pages reaches a threshold value.
A memory system, comprising:
- a first semiconductor memory module;
- and
- a processor configured to access the first semiconductor memory module by units of a page and further configured to execute fault handlings N times when an application driven by said processor is allocated to M pages, where M is a positive integer and N is a positive integer less than M;
- and
- wherein, when a number of the logical addresses and a number of the virtual addresses, which are mapped to each other by each of the fault handlings to be executed N times, reach a threshold value, the number of the logical addresses and the number of the virtual addresses are maintained.
A memory system, comprising:
- a first semiconductor memory module;
- and
- a processor configured to access the first semiconductor memory module by units of a page and further configured to execute fault handlings N times when an application driven by said processor is allocated to M pages, where M is a positive integer and N is a positive integer less than M;
- wherein said processor is configured to transmit a write command, a write address, a read command, and a read address to the first semiconductor memory module;
- and
- wherein said processor is further configured to inform the first semiconductor memory module about the logical addresses having a format different from a format of the write command and the write address, and a format of the read command and the read address.
Dependencies are inferred from the claim text.