Controller, operating method thereof and memory system for determining a low voltage detection fail
AssigneeSK hynix Inc.
InventorJeen Park
Life of this patent
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Abstract
A controller includes a power management unit suitable for providing and monitoring an operational voltage; a counter suitable for measuring a Low Voltage Detection (LVD) time, in which the operational voltage stays within an LVD range; a processor suitable for controlling a memory device to store write data with the LVD time corresponding to the write data stored into the memory device; and an LVD controller suitable for determining, during a recovery operation after occurrence of an LVD fail, a reason for a system fail as the LVD fail based on the LVD times and suitable for performing a debugging operation on a target data, which has the LVD time longer than a predetermined threshold time.
Claims19
A controller comprising:
- a power management unit suitable for providing and monitoring an operational voltage;
- a counter suitable for measuring a Low Voltage Detection (LVD) time, in which the operational voltage stays within an LVD range;
- a processor suitable for controlling a memory device to store write data with the LVD time corresponding to the write data stored into the memory device;
- and
- an LVD controller suitable for determining, during a recovery operation after occurrence of an LVD fail, a reason for a system fail as the LVD fail based on the LVD times and suitable for performing a debugging operation on a target data, which has the LVD time longer than a predetermined threshold time.
An operating method of a controller, the method comprising:
- monitoring, by a power management unit, an operational voltage;
- measuring, by a counter, a Low Voltage Detection (LVD) time, in which the operational voltage stays within an LVD range;
- controlling, by a processor, a memory device to store write data with the LVD time corresponding to the write data stored into the memory device;
- determining, by a LVD controller, a reason for a system fail as a LVD fail based on the LVD times during a recovery operation after occurrence of the LVD fail;
- and
- performing, by the LVD controller, a debugging operation on a target data, which has the LVD time longer than a predetermined threshold time.
A memory system comprising:
- a memory device;
- and
- a controller suitable for controlling the memory device,
- wherein the controller includes:
- a power management unit suitable for providing and monitoring an operational voltage;
- a counter suitable for measuring a Low Voltage Detection (LVD) time, in which the operational voltage stays within an LVD range;
- a processor suitable for controlling the memory device to store write data with the LVD time corresponding to the write data stored into the memory device;
- and
- an LVD controller suitable for determining, during a recovery operation after occurrence of an LVD fail, a reason for a system fail as the LVD fail based on the LVD times and suitable for performing a debugging operation on a target data, which has the LVD time longer than a predetermined threshold time.
A memory system comprising:
- a memory device suitable for storing data;
- and
- a controller suitable for using an operational voltage to program the data in the memory device,
- wherein the controller is suitable for measuring a Low Voltage Detection (LVD) time that the operational voltage is within an LVD range and storing the data with the LVD time associated with the data in the memory device,
- wherein the controller performs at least one of a first operation of determining a system fail based on the LVD times during a recovery operation and a second operation of performing a debugging operation to a target data associated with the LVD time longer than a threshold time.
Dependencies are inferred from the claim text.