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US 10,852,956 B1Granted
Structure of a high-bandwidth-memory command queue of a memory controller with external per-bank refresh and burst reordering
AssigneeCadence Design Systems, Inc.
InventorsYing Li, Xiaofei Li, Yanjuan Zhan, Zhehong Qian, Buying Du
Life of this patent
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Abstract
Embodiments of the invention provide a novel structure of a high-bandwidth-memory command queue of a memory controller with external per-bank refresh and DRAM burst reordering. Where the external per-bank refresh removes some of the unpredictable nature of PBR commands and DRAM burst reordering provides for efficient utilization of memory bandwidth.
Claims20
A memory controller comprising at least:
- a per-bank refresh interface, the per-bank refresh interface receiving one or more per-bank refresh commands from a requesting apparatus external to the memory controller;
- a system bus interface, the system bus interface receiving one or more memory access commands from the requesting apparatus external to the memory controller, the requesting apparatus generating the one or more per-bank refresh commands and the one or more memory access commands;
- and
- a command queue, the command queue comprising at least one or more storage elements, the storage elements storing one or more per-bank refresh commands and one or more memory access commands from the requesting apparatus external to the memory controller.
1 more element
A method, comprising:
- receiving one or more per-bank refresh commands from a requesting apparatus external to a memory controller, the one or more per-bank refresh commands received at a per-bank refresh interface of the memory controller;
- receiving one or more memory access commands from the requesting apparatus external to the memory controller, the one or more memory access commands received at a system bus interface of the memory controller, the requesting apparatus generating the one or more per-bank refresh commands and the one or more memory access commands;
- and
- generating one or more entries in a command queue of the memory controller comprising at least one or more storage elements, the one or more entries in the command queue corresponding to the one or more per-bank refresh commands and the one or more memory access commands from the requesting apparatus external to the memory controller.
1 more element
Dependencies are inferred from the claim text.