Adaptive power down of intra-chip interconnect

An integrated circuit, comprising:

• a plurality of last-level caches that can be placed in at least a high cache-power consumption mode and a low cache-power consumption mode, the plurality of last-level caches including a first last-level cache and a second last-level cache;
• a plurality of processor cores configured to access data in the plurality of last-level caches;
• and
• an interconnect network, comprised of a plurality of links that can be placed in at least a high link-power consumption mode and a low link-power consumption mode, the interconnect network configured to receive access addresses from the plurality of processor cores and to couple, via respective subsets of the plurality of links, each of the plurality of processor cores to a respective one of the plurality of last-level caches, and to cause a first subset of the plurality of links to be placed in the low link-power consumption mode based at least in part on the first last-level cache being in the low cache-power consumption mode.