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US 10,852,809 B2Granted
Power saving techniques for memory systems by consolidating data in data lanes of a memory bus
AssigneeQUALCOMM Incorporated
InventorsJungwon Suh, Dexter Tamio Chun, Michael Hawjing Lo
Life of this patent
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Abstract
Power saving techniques for memory systems are disclosed. In particular, exemplary aspects of the present disclosure contemplate taking advantage of patterns that may exist within memory elements and eliminating duplicative data transfers. Specifically, if data is repetitive, instead of sending the same data repeatedly, the data may be sent only a single time with instructions that cause the data to be replicated at a receiving end to restore the data to its original repeated state.
Claims27
An apparatus, comprising:
- a host processor, the host processor comprising:
- a physical layer (PHY) interface configured to be coupled to a plurality of data lanes of a memory bus including a data mask (DM) lane;
- a read register;
- and
- a memory controller coupled to the PHY interface, wherein the memory controller is configured to:
- cause data within the read register to be duplicated based on information received through the DM lane.
3 more elements
An apparatus comprising:
- a memory system comprising:
- an input/output (IO) block configured to be coupled to a memory bus;
- a memory bank comprising memory elements, the memory bank communicatively coupled to the IO block;
- and
- a data pattern checker logic circuit configured to determine if patterns of repeatable data exist in data read from the memory elements and consolidate the data and send the data across only certain ones of a plurality of data lanes of the memory bus,
- wherein the memory system is configured to send information to a memory controller in a host through a data mask (DM) lane of the memory bus, indicating how the data has been consolidated onto only certain ones of the plurality of data lanes of the memory bus.
3 more elements
An apparatus, comprising:
- a host processor, the host processor comprising:
- a physical layer (PHY) interface configured to be coupled to a plurality of data lanes of a memory bus;
- and
- a memory controller coupled to the PHY interface, the memory controller comprising a data pattern checker logic circuit, wherein the memory controller is configured to:
- use the data pattern checker logic circuit to determine if patterns of repeatable data exist in data to be written to a memory element over the memory bus;
- and
- consolidate the data and send the data across only certain ones of the plurality of data lanes of the memory bus using a write command modified by a column address select (CAS) command, wherein the CAS command informs the memory element how to duplicate the data.
4 more elements
An apparatus comprising:
- a memory system comprising:
- an input/output (IO) block configured to be coupled to a memory bus;
- a memory bank comprising memory elements, the memory bank communicatively coupled to the IO block;
- and
- a write register operative to receive data from the memory bus through the IO block and duplicate the data a number of times according to a write command modified by a column address select (CAS) command from a host processor, wherein the CAS command informs the memory system how to duplicate the data based on a data repeating pattern between data lanes.
2 more elements
Dependencies are inferred from the claim text.