Hybrid powering off of storage component memory cells

A method comprising:

• receiving, from an integrated circuit, an integrated circuit power enable signal indicating whether the integrated circuit determines that memory cells of a storage component are to be powered on;
• receiving, from a storage controller of the storage component, a storage controller power enable signal indicating whether the storage controller determines that the memory cells of the storage component are to be powered on, wherein the storage controller is configured to manage storage of data in the memory cells of the storage component and retrieval of data from the memory cells of the storage component;
• in an instance when both the integrated circuit power enable signal and the storage controller power enable signal indicate that the memory cells are to be powered on, powering on the memory cells;
• and
• in another instance when the integrated circuit power enable signal indicates that the memory cells are to be powered on and the storage controller power enable signal indicates that the memory cells are to be powered off, overriding the integrated circuit power enable signal and powering off the memory cells.

A system comprising:

• a plurality of memory cells;
• an integrated circuit having as an output an integrated circuit power enable signal;
• a storage controller configured to manage storage of data in the plurality of memory cells and retrieval of data from the plurality of memory cells, the storage controller having as an output a first storage controller power enable signal;
• a first logic component, coupled to the storage controller and the integrated circuit, having as inputs the integrated circuit power enable signal from the integrated circuit and the first storage controller power enable signal, the first logic component having as an output a first switch control line having a first state or a second state that is based on the integrated circuit power enable signal and the first storage controller power enable signal;
• and
• a first power switch, coupled to the first logic component, having as inputs a first input power line and the first switch control line, the first power switch having an output to provide power from the first input power line to the plurality of memory cells in response to the first switch control line having the first state, and to provide no power from the first input power line to the plurality of memory cells in response to the first switch control line having the second state,
• the first logic component being configured to enable the first storage controller power enable signal from the storage controller to override the integrated circuit power enable signal from the integrated circuit and place the first switch control line into the second state in an instance when the integrated circuit power enable signal indicates that power should be provided to the plurality of memory cells.