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US 10,852,806 B2Granted
Dual path sequential element to reduce toggles in data path
AssigneeIntel Corporation
InventorsSubramaniam Maiyuran, Sanjeev S. Jahagirdar, Kiran C. Veernapu, Eric J. Asperheim, Altug Koker, Balaji Vembu, Joydeep Ray, Abhishek R. Appu
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Abstract
Methods and apparatus relating to techniques for a dual path sequential element to reduce toggles in data path are described. In an embodiment, switching logic causes signals for a single data path of a processor to be directed to at least two separate data paths. At least one of the two separate data paths is power gated to reduce signal toggles in the at least one data path. Other embodiments are also disclosed and claimed.
Claims20
An apparatus comprising:
- switching logic circuitry to cause signals for a single data path of a processor to be directed to at least two separate data paths of the processor,
- wherein one or more of a plurality of flops in the at least two separate data paths of the processor are to be bypassed in response to a determination that the processor is to run at a first frequency instead of a second frequency, wherein the processor is to run at the first frequency after the one or more of the plurality of the flops in the at least two separate data paths of the processor are bypassed,
- wherein the first frequency is lower than the second frequency.
A computing system comprising:
- a processor, having one or more processors;
- and
- memory, coupled to the processor, to store one or more instructions to be executed by the processor,
- the processor comprising switching logic circuitry to cause signals for a single data path of the processor to be directed to at least two separate data paths of the processor,
- wherein one or more of a plurality of flops in the at least two separate data paths of the processor are to be bypassed in response to a determination that the processor is to run at a first frequency instead of a second frequency, wherein the processor is to run at the first frequency after the one or more of the plurality of the flops in the at least two separate data paths of the processor are bypassed,
- wherein the first frequency is lower than the second frequency.
3 more elements
Dependencies are inferred from the claim text.