US 10,852,648 B2Granted

Mask pattern correction system, and semiconductor device manufacturing method utilizing said correction system

AssigneeToshiba Memory Corporation

InventorsKazuyuki Hino, Hiromitsu Mashita, Masahiro Miyairi, Hiroshi Yoshimura, Taiga Uno, Sachiyo Ito, Shinichirou Ooki, Kenji Shiraishi, Hirotaka Ichikawa, Yuto Takeuchi

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Abstract

According to one embodiment, a mask pattern correction system includes the following configuration. A stress analysis circuitry divides a layout of a circuit pattern formed using a design mask formed in accordance with mask design data into correction regions, and acquires a displacement amount from the regions. A correction value calculation circuitry calculates a displacement correction value from the displacement amount. A correction map generation circuitry generates a correction map based on a correction value difference of the displacement correction values. A mask position correction circuitry allocates the regions to a layout of the circuit pattern, performs displacement correction of a mask pattern on the design mask by the displacement correction values, and creates a correction mask based on the displacement correction.

Claims18

Dependent claims

A mask pattern correction system comprising:

a stress analysis circuitry configured to divide a layout of a first circuit pattern formed on a substrate using a design photo mask formed in accordance with mask design data into a plurality of correction regions, and to acquire a displacement amount by a stress analysis from measurement data including position information of the correction regions;
a correction value calculation circuitry configured to calculate a displacement correction value in the correction regions from the displacement amount;
a correction map generation circuitry configured to generate a correction map including the correction regions based on a first correction value difference of the displacement correction values between the correction regions that are mutually adjacent in the correction regions;
and
a mask position correction circuitry configured to allocate the correction regions in the correction map to a layout of the first circuit pattern, to perform displacement correction of a mask pattern on the design photo mask by the displacement correction values, and to create a correction photo mask based on the displacement correction.

2 more elements

A semiconductor device manufacturing method comprising:

dividing a layout of a first circuit pattern formed on a substrate using a design photo mask formed in accordance with mask design data, into a plurality of correction regions;
acquiring a displacement amount by a stress analysis from measurement data including position information of the correction regions;
calculating a displacement correction value in the correction regions from the displacement amount;
generating a correction map including the correction regions based on a first correction value difference of the displacement correction values between the correction regions that are mutually adjacent in the correction regions;
allocating the correction regions in the correction map to a layout of the first circuit pattern;
performing displacement correction of a mask pattern on the design photo mask from the displacement correction values;
and
forming a correction photo mask based on the displacement correction.

5 more elements

A non-transitory computer readable storage medium storing a program, the program enabling steps comprising:

dividing a layout of a first circuit pattern formed on a substrate using a design photo mask formed in accordance with mask design data, into a plurality of correction regions;
acquiring a displacement amount by a stress analysis from measurement data including position information of the correction regions;
calculating a displacement correction value in the correction regions from the displacement amount;
generating a correction map including the correction regions based on a first correction value difference of the displacement correction values between the correction regions that are mutually adjacent in the correction regions;
and
allocating the correction regions in the correction map to a layout of the first circuit pattern;
performing displacement correction of a mask pattern on the design photo mask from the displacement correction values;
and
forming a correction photo mask based on the displacement correction.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/566,363Filed 10 Sep 2019
Priority: JP 2018-19138410 Oct 2018
Published: US 2020/0117104 A116 Apr 2020
Granted: 1 Dec 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G03F 1/70
Preparation processes not covered by groups G03F1/20 - G03F1/50: adapting basic layout or design of masks to lithographic process requirements,…
G03F 7/70783
Handling of masks or workpieces: handling stress or warp of chucks, masks or workpieces, e.g. to compensate for imaging errors or considerations…
G03F 1/36
Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles…
G03F 1/72
Preparation processes not covered by groups G03F1/20 - G03F1/50: repair or correction of mask defects