Method of minimizing errors of optical proximity correction in semiconductor pattern and device for performing the same
AssigneeSamsung Electronics Co., Ltd.
InventorsMoo Joon Shin, Kyung Jae Park
Life of this patent
Estimating the term…
Abstract
In a method for minimizing optical proximity correction errors in a semiconductor pattern. The method includes modifying a mask in a quantized unit to reduce an edge placement error between a simulation layout shape and a target layout shape; adjusting a critical dimension (CD) error between a CD of the simulation layout shape and a CD of the target layout shape to generate an adjusted CD error by further modifying at least one side of the mask in a predetermined unit; and reforming the simulation layout shape by modifying each side of the mask with arbitrary correction values.
Claims20
A method for minimizing optical proximity correction errors in a semiconductor pattern, the method comprising:
- modifying a mask in a quantized unit into a first intermediate mask to reduce an edge placement error between a simulation layout shape and a target layout shape, the target layout shape being a designed layout pattern, the simulation layout shape being a layout pattern formed by light passing through the mask in a simulation process, and the edge placement error including a critical dimension (CD) error corresponding to a difference between a CD of the simulation layout shape and a CD of the target layout shape at two opposite edges of the simulation layout shape and the target layout shape;
- adjusting the CD error in the edge placement error between the CD of the simulation layout shape and the CD of the target layout shape to generate an adjusted CD error by further modifying at least one side of the first intermediate mask in a predetermined unit according to a comparison result into a second intermediate mask, the comparison result being obtained by comparing an absolute value of the CD error between the CD of the simulation layout shape and the CD of the target layout shape with a predetermined error threshold value;
- and
- reforming the simulation layout shape by modifying each side of the second intermediate mask with arbitrary correction values into a third intermediate mask.
A device for minimizing optical proximity correction errors in a semiconductor pattern, the device comprising:
- an EPE corrector to modify a mask in a quantized unit to reduce an edge placement error between a simulation layout shape and a target layout shape, the edge placement error including a critical dimension (CD) error corresponding to a difference between a CD of the simulation layout shape and a CD of the target layout shape at two opposite edges of the simulation layout shape and the target layout shape;
- a CD corrector to compare an absolute value of the CD error between the CD of the simulation layout shape and the CD of the target layout shape, which is derived by modifying the mask in the EPE corrector, with a predetermined error threshold value to generate a comparison result and to further modify at least one side of the mask in a predetermined unit according to the comparison result to obtain an adjusted CD error;
- and
- a shape disturbancer to modify each side of the mask with arbitrary correction values to reform the simulation layout shape.
Dependencies are inferred from the claim text.