Devices, systems and methods for digitally transporting signals in GNSS repeater systems using CPRI

A global navigation satellite system (GNSS) repeater system for improving phase and frequency alignment of radio frequency (RF) signals transported through fiber optic communication channels, the GNSS repeater system comprising:

• an RF antenna for acquiring an RF signal and relaying the acquired RF signal to a remote outdoor unit, wherein the RF signal comprises a global positioning system (GPS) signal;
• a remote outdoor unit coupled to the RF antenna, the remote outdoor unit comprising a signal processor, a GNSS receiver, a software defined radio (SDR), a multiple-output clock synthesizer, a field-programmable gate array (FPGA), and a first small form-factor pluggable (SFP) port, wherein:
• the signal processor is configured to pre-condition the acquired RF signal received from the RF antenna,
• the GNSS receiver is configured to process the pre-conditioned RF signal and output a GPS-disciplined clock signal,
• the multiple-output clock synthesizer is configured to process the GPS-disciplined clock signal and generate a system clock signal,
• the SDR is configured to digitize the pre-conditioned RF signal into in-phase and quadrature (I/Q) antenna data,
• the FPGA is configured to process the I/Q antenna data into a digital signal formatted into a common public radio interface (CPRI) frame, generate a timestamp based on the system clock signal, and insert the timestamp into a proprietary field of the CPRI frame, and
• the first SFP port is configured to convert the digital signal comprising the formatted CPRI frame into an optical signal comprising the CPRI frame, and output the optical signal comprising the CPRI frame;
• a fiber optic communication channel for transporting the optical signal comprising the CPRI frame;
• and
• an indoor head end unit, coupled to the remote outdoor unit over the fiber optic communication channel, the indoor head end unit comprising a second SFP port, a second FPGA, a second multiple-output clock synthesizer, a second SDR, a second signal processor, and a head end output port, wherein:
• the second SFP port is configured to receive the optical signal comprising the CPRI frame, and convert the optical signal comprising the CPRI frame into a recovered digital signal,
• the second FPGA is configured to extract the CPRI frame from the recovered digital signal, extract the timestamp from the CPRI frame, decode the CPRI frame into recovered I/Q antenna data, and output the timestamp and recovered I/Q antenna data,
• the second multiple-output clock synthesizer is configured to generate a recovered clock signal, and the recovered clock signal is output to the second FPGA, the second SDR, and the second signal processor,
• the second SDR is configured to create a reconstructed RF signal based on the recovered I/Q antenna data,
• the second signal processor is configured to condition the reconstructed RF signal, and
• the head end output port is configured to output the conditioned reconstructed RF signal,
• wherein the timestamp inserted in the CPRI frame is used to determine the communication delay between the remote outdoor unit and the indoor head end unit, and
• wherein the reconstructed RF signal has phase and frequency characteristics in alignment with the acquired RF signal.