System and method for accelerating real X detection in gate-level logic simulation
AssigneeAvery Design Systems, Inc.
InventorKai-Hui Chang
Life of this patent
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Abstract
A computer executable tool analyzes Boolean logic in a gate-level netlist with simulated values and efficiently determines whether a subset of the netlist produces real Xs or not. If whether the netlist produces real Xs or not cannot be quickly determined, further formal analysis needs to be performed, and this step can be time-consuming. By quickly determining whether real Xs are produced, the use of time-consuming formal methods can be reduced, thus reducing X-pessimism analysis time.
Claims19
A method for correcting gate-level simulation, comprising:
- identifying unknown values (Xs) that are false when simulating a given trace of a design netlist;
- determining a sub-circuit of the design netlist for each false X having inputs of real Xs and an output of a false X;
- generating code to correct each false X in simulation based on the sub-circuit to eliminate false Xs in simulation of the design netlist;
- converting the sub-circuit into an And-Inverter-Graph (AIG);
- calculating a structure-based hash number associated with the AIG;
- and
- looking up at least one vector from a vector database using the hash number.
A system for correcting gate-level simulation, comprising:
- a memory having program instructions stored thereon;
- and
- a processor configured to:
- identify unknown values (Xs) that are false when simulating a given trace of a design netlist;
- determine a sub-circuit of the design netlist for each false X having inputs of real Xs and an output of a false X;
- generate code to correct each false X in simulation based on the sub-circuit to eliminate false Xs in simulation of the design netlist;
- convert the sub-circuit into an And-Inverter-Graph (AIG);
- calculate a structure-based hash number associated with the AIG;
- and
- look up at least one vector from a vector database using the hash number.
A method for determining if a sub-circuit generates constant value, comprising:
- determining whether outputs of a sub-circuit in a simulation are constant;
- converting the sub-circuit into an And-Inverter-Graph (AIG);
- calculating a structure-based hash number associated with the AIG;
- looking up at least one vector from a vector database using the hash number;
- and
- simulating the AIG using the at least one vector to determine sub-circuit output status.
A system for determining if a sub-circuit generates constant value, comprising:
- a memory having program instructions stored thereon;
- and
- a processor configured to:
- determine whether outputs of a sub-circuit in a simulation are constant;
- convert the sub-circuit into an And-Inverter-Graph (AIG);
- calculate a structure-based hash number associated with the AIG;
- look up at least one vector from a vector database using the hash number;
- and
- simulate the AIG using the at least one vector to determine sub-circuit output status.
Dependencies are inferred from the claim text.