System and method to secure FPGA card debug ports

A system for securing access to a debug port of an FPGA (Field Programmable Gate Array) card installed in an Information Handling System (IHS), the system comprising:

• a remote access controller configured to monitor operations of the IHS, the remote access controller configured to:
• issue a query to a management controller of the FPGA card to determine a status of the FPGA card debug port;
• generate a passcode for the debug port, wherein the passcode is generated by hashing a serial number of the FPGA card concatenated with a service tag of the IHS;
• disable the debug port via a message to the management controller;
• receive a request for access to the debug port, wherein the request includes a requestor password;
• authorize access to the debug port by the requestor, if the requestor password matches the generated passcode;
• and
• disable the debug port upon the next power cycle of the FPGA card;
• and
• the management controller configured to:
• determine the status of the debug port in response to the query from the remote access controller;
• detect the coupling of a device to the debug port;
• receive a request from the device for the requestor to access the debug port, wherein the request includes the requestor password;
• and
• enable the debug port upon the authorization of the remote access controller.

A remote access controller configured for securing access to an FPGA (Field Programmable Gate Array) card debug port, the remote access controller configured to:

• determine a status of the FPGA card debug port via a query to a management controller of the FPGA card;
• detect a coupling of a device to the debug port;
• generate a passcode for the debug port, wherein the passcode is generated by hashing a serial number of the FPGA card concatenated with a service tag of the IHS (Information Handling System) in which the FPGA card is installed;
• disable the debug port via a message to the management controller;
• detect a request for access to the debug port by a requestor, wherein the request includes a requestor password;
• provide the requestor access to the debug port if the requestor password matches the generated passcode;
• and
• disable the debug port upon the next power cycle of the FPGA card.