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US 10,852,337 B2Granted
Test structures for measuring silicon thickness in fully depleted silicon-on-insulator technologies
AssigneePDF Solutions, Inc.
InventorsSharad Saxena, Tomasz Brozek, Yuan Yu, Mike Kyu Hyon Pak, Meindert Martin Lunenborg
Life of this patent
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Abstract
Described are test structures and methods for measuring silicon thickness in fully depleted silicon-on-insulator technologies.
Claims8
An apparatus for determining a thickness of a fully depleted silicon-on-insulator layer disposed in a CMOS integrated circuit, the apparatus being disposed on a FDSOI substrate that also includes the CMOS integrated circuit, the apparatus comprising:
- a test structure that includes at least one test circuit, the at least one test circuit including an isolated fully depleted silicon-on-insulator layer disposed above an isolated buried oxide layer and a gate dielectric disposed above the isolated fully depleted silicon-on-insulator layer and which further includes a first Epi region surrounding the isolated fully depleted silicon-on-insulator layer to bias the isolated fully depleted silicon-on-insulator layer, the test structure further including:
- a total capacitance measurement circuit configured to output a total capacitance measurement, the total capacitance measurement circuit including a first terminal connected to the gate dielectric disposed above the isolated fully depleted silicon-on-insulator layer and a second terminal connected to one of an n-well and a p-well, for obtaining the total capacitance measurement;
- a gate dielectric capacitance measurement circuit configured to output a gate dielectric capacitance measurement, the gate dielectric capacitance measurement circuit including the first terminal connected to the gate dielectric and a third terminal connected to source/drain regions disposed adjacent the isolated fully depleted silicon-on-insulator layer and the second terminal connected to one of an n-well and p-well, for obtaining the gate dielectric capacitance measurement;
- and
- a buried oxide capacitance measurement circuit configured to output a buried oxide capacitance measurement, the buried oxide capacitance measurement circuit including the first terminal connected to the gate dielectric and the second terminal connected to one of an n-well and p-well, for obtaining the buried oxide capacitance measurement.
2 more elements
Dependencies are inferred from the claim text.