Probabilistic shaping techniques for high performance coherent optical transceivers

A method of operating a communication device having a distribution matcher encoder module and a distribution matcher decoder module electrically coupled by a channel module, the method comprising:

• receiving, by n encoder function blocks of the distribution matcher encoder module coupled in series and configured to convert data from a first form (x) to a second form (b) using an encoder lookup table (LUT), the following inputs:
• data x, a code length n, and a bits per codeword n′;
• storing, by a plurality of encoder storage units of the series of encoder function blocks, the following initial values:
• an=x and nn′=n′;
• performing, by the series of encoder function blocks, the following actions for i=n−1 to 0:
• wherein ti [n] is the function to access the encoder LUT;
• when a first condition characterized by ai+1≥ti [ni+1′−1] or a second condition characterized by ni+1′≤0 is satisfied, computing, by encoder comparison and adder circuits of the series of encoder function blocks, and storing, by the plurality of encoder storage units, the following intermediate values:
• ai=ai+1−ti[ni+1′−1], bi=0, and ni′=ni+1′;
• and
• when neither the first condition nor the second condition is satisfied, computing, by the encoder comparison and adder circuits, and storing, by the plurality of encoder storage units, the following intermediate values:
• ai=ai+1, bi=1, and ni′=ni+1′−1;
• outputting, by the series of encoder function blocks, converted data b;
• receiving, by n decoder function blocks of the distribution matcher decoder module coupled in series and configured to convert data from the second form to the first form using a decoder LUT, the converted data b, the code length n, and the bits per codeword n′ as inputs;
• storing, by a plurality of decoder storage units of the series of decoder function blocks, the following initial values:
• an=0 and nn′=n′;
• performing, by the series of decoder function blocks, the following actions for i=n−1 to 0:
• wherein ti [n] is the function to access the decoder LUT;
• when a first condition characterized by bi==1 or a second condition characterized by ni+1′==0 is satisfied, computing, by decoder comparison and adder circuits of the series of decoder function blocks, and storing, by the plurality of decoder storage units, the following intermediate value:
• ai=ai+1;
• when neither the first condition nor the second condition is satisfied, computing, by the decoder comparison and adder circuits, and storing, by the plurality of decoder storage units, the following intermediate value:
• ai=ai+1+ti [ni+1′−1];
• when the first condition is satisfied, computing, by the decoder comparison and adder circuits, and storing, by the plurality of decoder storage units, the following intermediate value:
• ni′=ni+1′−1;
• and
• when the first condition is not satisfied, computing, by the decoder comparison and adder circuits, and storing, by the plurality of decoder storage units, the following intermediate value:
• ni′=ni+1′;
• storing, by the plurality of decoder storage units, the following final value:
• x=a0;
• and
• outputting, by the series of decoder function blocks, restored data x.

A method of operating a communication device having a distribution matcher encoder module and a distribution matcher decoder module electrically coupled by a channel module, the method comprising:

• receiving, by n encoder function blocks of the distribution matcher encoder module coupled in series and configured to convert data from a first form (x) to a second form (b) using an encoder lookup table (LUT), the following inputs:
• data x and a code length n;
• storing, by a plurality of encoder storage units of the series of encoder function blocks, the following initial value:
• n′=0;
• performing, by the series of encoder function blocks, the following actions while
• (
• x
• ≥
• ⁢
• (
• n
• n
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• )
• )
• :
• computing, by encoder comparison and adder circuits of the series of encoder function blocks, and storing, by the plurality of encoder storage units, the following intermediate value:
• x
• =
• x
• -
• (
• n
• n
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• ;
• and
• computing, by the encoder comparison and adder circuits, and storing, by the plurality of encoder storage units, the following intermediate value:
• n′=n′+1;
• computing, by the encoder comparison and adder circuits, and storing, by the plurality of encoder storage units, the following intermediate value:
• an=x;
• performing, by the series of encoder function blocks, the following actions for i=n−1 to 0:
• wherein ti [n] is the function to access the encoder LUT;
• when a first condition characterized by ai+1≥ti[n′−1] or a second condition characterized by n′≤0 is satisfied, computing, by the encoder comparison and adder circuits, and storing, by the plurality of encoder storage units, the following intermediate values:
• ai=ai+1−ti[n′−1] and bi=0;
• and
• when neither the first condition nor the second condition is satisfied, computing, by the encoder comparison and adder circuits, and storing, by the plurality of encoder storage units, the following intermediate values:
• ai=ai+1, bi=1, and n′=n′−1;
• outputting, by the series of encoder function blocks, converted data b;
• receiving, by n decoder function blocks of the distribution matcher decoder module coupled in series and configured to convert data from the second form to the first form using a decoder LUT, the converted data b and the code length n as inputs;
• computing, by decoder comparison and adder circuits of the series of decoder function blocks, and storing, by a plurality of decoder storage units of the series of decoder function blocks, the following initial values:
• nn′=ωH(b), where ωH(b) is the Hamming weight of b;
• and
• a
• n
• =
• ∑
• k
• =
• 1
• ω
• H
• ⁡
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• b
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• ⁢
• (
• n
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• ;
• performing, by the series of decoder function blocks, the following actions for i=n−1 to 0:
• wherein ti [n] is the function to access the decoder LUT;
• when a first condition characterized by bi==1 or a second condition characterized by ni+1′==0 is satisfied, computing, by the decoder comparison and adder circuits, and storing, by the plurality of decoder storage units, the following intermediate value:
• a1=ai+1;
• when neither the first condition nor the second condition is satisfied, computing, by the decoder comparison and adder circuits, and storing, by the plurality of decoder storage units, the following intermediate value:
• ai=ai+1+ti[ni+1′−1];
• when the first condition is satisfied, computing, by the decoder comparison and adder circuits, and storing, by the plurality of decoder storage units, the following intermediate value:
• ni′=ni+1′−1;
• and
• when the first condition is not satisfied, computing, by the decoder comparison and adder circuits, and storing, by the plurality of decoder storage units, the following intermediate value:
• ni′=ni+1′;
• and
• outputting, by the series of decoder function blocks, restored data x.