Low power digital interpolation/decimation apparatus and method

A method for performing interpolation in a digital circuit that receives an input signal, comprising:

• wherein the digital circuit includes a plurality of upsampling stages and filtering stages used to perform the interpolation;
• wherein a first path comprises a first portion of the plurality of upsampling stages and filtering stages, and a second path comprises a second portion of the plurality of upsampling stages and filtering stages distinct from the first portion;
• wherein the first path consumes less quiescent state power than the second path;
• determining a spectral content of the input signal;
• and
• using the first or second path and turning off the unused first or second path based on the spectral content.

An apparatus for performing interpolation in a digital circuit that receives an input signal, comprising:

• a plurality of upsampling stages and filtering stages used to perform interpolation;
• wherein a first path comprises a first portion of the plurality of upsampling stages and filtering stages, and a second path comprises a second portion of the plurality of upsampling stages and filtering stages distinct from the first portion;
• wherein the first path consumes less quiescent state power than the second path;
• wherein the second path has higher filtering performance than the first path;
• and
• a selection circuit configured to use the first or second path and turn off the unused first or second path based on a level of the input signal.

A method for performing interpolation in a digital circuit that receives an input signal, comprising:

• wherein the digital circuit includes a plurality of upsampling stages and filtering stages used to perform interpolation;
• wherein a first path comprises a first portion of the plurality of upsampling stages and filtering stages, and a second path comprises a second portion of the plurality of upsampling stages and filtering stages distinct from the first portion;
• wherein the first path consumes less quiescent state power than the second path;
• wherein the second path has higher filtering performance than the first path;
• and
• using the first or second path and turning off the unused first or second path based on a level of the input signal.

An apparatus for performing decimation in a digital circuit that receives an input signal, comprising:

• a plurality of downsampling stages and filtering stages used to perform decimation;
• wherein a first path comprises a first portion of the plurality of downsampling stages and filtering stages, and a second path comprises a second portion of the plurality of downsampling stages and filtering stages distinct from the first portion;
• wherein the first path consumes less quiescent state power than the second path;
• and
• a selection circuit configured to:
• determine a spectral content of the input signal;
• and
• use the first or second path and turn off the unused first or second path based on the spectral content.

A method for performing decimation in a digital circuit that receives an input signal, comprising:

• wherein a plurality of downsampling stages and filtering stages used to perform decimation;
• wherein a first path comprises a first portion of the plurality of downsampling stages and filtering stages, and a second path comprises a second portion of the plurality of downsampling stages and filtering stages distinct from the first portion;
• wherein the first path consumes less quiescent state power than the second path;
• and
• determining a spectral content of the input signal;
• and
• using the first or second path and turning off the unused first or second path based on the spectral content.

An apparatus for performing decimation in a digital circuit that receives an input signal, comprising:

• a plurality of downsampling stages and filtering stages used to perform decimation;
• wherein a first path comprises a first portion of the plurality of downsampling stages and filtering stages, and a second path comprises a second portion of the plurality of downsampling stages and filtering stages distinct from the first portion;
• wherein the first path consumes less quiescent state power than the second path;
• and
• a selection circuit configured to use the first or second path and turn off the unused first or second path based on a level of the input signal.

A method for performing decimation in a digital circuit that receives an input signal, comprising:

• wherein a plurality of downsampling stages and filtering stages used to perform decimation;
• wherein a first path comprises a first portion of the plurality of downsampling stages and filtering stages, and a second path comprises a second portion of the plurality of downsampling stages and filtering stages distinct from the first portion;
• wherein the first path consumes less quiescent state power than the second path;
• and
• using the first or second path and turning off the unused first or second path based on a level of the input signal.