Discrete time IIR filter with high stop band rejection

A pipelined charge rotating discrete time analog filter, comprising:

• an input node for receiving an input signal;
• a first history capacitor array coupled to said input node;
• a plurality of switch banks coupled to said first history capacitor array, each switch bank comprising:
• a non-switched sampling capacitor coupled to a reset switch and configured to share charge with said first history capacitor array;
• a plurality of second history capacitor arrays coupled to and configured to cyclically share charge with the sampling capacitor in each respective switch bank, each first and second history capacitor array operative to perform charge sharing among its elements, wherein said first and second history capacitor arrays are not reset from cycle to cycle;
• wherein during each multi-phase cycle of said filter, each second history capacitor array individually connected to its respective sampling capacitor such that only a single second history capacitor array is connected to said sampling capacitor during each phase;
• wherein while a second history capacitor array is connected to its respective sampling capacitor, its capacitance is dynamically changed thereby delivering charge nonuniformly in a plurality of steps;
• and
• wherein an output node coupled to one of said history capacitors arrays in a switch bank generates a filtered output signal once each phase period.

A method of analog charge rotating filtering in discrete time, the method comprising:

• receiving an input signal;
• charging a first history capacitor array with said input signal;
• sharing charge with a sampling capacitor coupled to said first history capacitor array;
• cyclically sharing charge between said sampling capacitor and a plurality of second history capacitor arrays, each first and second history capacitor array operative to perform charge sharing among its elements;
• wherein during each multi-phase cycle of said filter, each second history capacitor array is individually connected to said sampling capacitor such that only a single second history capacitor array is connected to said sampling capacitor during each phase;
• wherein an output node coupled to one of said second history capacitors arrays generates a filtered output signal once each cycle;
• and
• wherein while each history capacitor array is connected to said sampling capacitor, its capacitance is dynamically changed during multiple sub-phases of said multi-phase cycle thereby delivering charge nonuniformly in a plurality of steps.

A pipelined charge rotating discrete time analog filter, comprising:

• an input node for receiving an input signal;
• a first history capacitor array coupled to said input node;
• a plurality of switch banks coupled to said first history capacitor, each switch bank comprising:
• a first switch coupled to said input signal;
• a sampling capacitor coupled to said first switch and to a reset switch, said sampling capacitor configured to cyclically share charge with a plurality of history capacitor arrays during each cycle of the filter;
• a plurality of second switches coupled to a plurality of second history capacitor arrays, each switch coupled to said sampling capacitor and to a respective second history capacitor array;
• wherein during each multi-phase cycle of said filter, each history capacitor array is individually connected to its respective sampling capacitor such that only a single history capacitor array in each switch bank is connected to its respective sampling capacitor during each phase;
• wherein an output node coupled to one of said second history capacitors arrays generates a filtered output signal once each phase period;
• and
• wherein while a history capacitor array is connected to said sampling capacitor in a respective switch bank, its capacitance is increased during multiple sub-phases of said multi-phase cycle.