US 10,840,052 B2 · Planar gate-insulated vacuum channel transistor

Abstract

A current CMOS technology compatible process to create a planar gate-insulated vacuum channel semiconductor structure. In one example, the structure is created on highly doped silicon. In another example, the structure is created on silicon on insulator (SOI) over a box oxide layer. The planar gate-insulated vacuum channel semiconductor structure is formed over a planar complementary metal-oxide-semiconductor (CMOS) device with a gate stack and a tip-shaped SiGe source/drain region. Shallow trench isolation (STI) is used to form cavities on either side of the gate stack. The cavities are filled with dielectric material. Multiple etching techniques disclosed creates a void in a channel in the tip-shaped SiGe source/drain region under the gate stack. A vacuum is created in the void using physical vapor deposition (PVD) in a region above the tip-shaped SiGe source/drain regions.

Claims14

Dependent claims

A method of forming a planar gate-insulated vacuum channel semiconductor structure, the method comprising:

depositing a conformal hard mask liner over a planar complementary metal-oxide-semiconductor (CMOS) device with a gate stack and a tip-shaped SiGe source/drain region that extend laterally beneath each side of the gate stack;
using shallow trench isolation (STI) to form cavities directly beneath the gate stack;
filling the cavities with dielectric material using oxide deposition;
performing chemical-mechanical planarization (CMP) to a height of the conformal hard mask liner;
performing a first etching using reactive-ion etching along a first direction cutting the gate stack from a top direction down to the tip-shaped SiGe source/drain region;
performing a second etching using wet etching along a second direction perpendicular to the first direction to create a void in a channel in the tip-shaped SiGe source/drain region under the gate stack;
and
creating a vacuum in the void using physical vapor deposition (PVD) in a region above the tip-shaped SiGe source/drain regions.

5 more elements

A computer program product for generating integrated circuit designs according to design rules, the integrated circuit designs comprising a planar gate-insulated vacuum channel semiconductor structure, the computer program product comprising a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code, when executed by a processor, cause the processor to perform:

depositing a conformal hard mask liner over a planar complementary metal-oxide-semiconductor (CMOS) device with a gate stack and a tip-shaped SiGe source/drain region that extend laterally beneath each side of the gate stack;
using shallow trench isolation (STI) to form cavities directly beneath the gate stack;
filling the cavities with dielectric material using oxide deposition;
performing chemical-mechanical planarization (CMP) to a height of the conformal hard mask liner;
performing a first etching using reactive −ion etching along a first direction cutting the gate stack from a top direction down to the tip-shaped SiGe source/drain region;
performing a second etching using wet etching along a second direction perpendicular to the first direction to create a void in a channel in the tip-shaped SiGe source/drain region under the gate stack;
and creating a vacuum in the void using physical vapor deposition (PVD) in a region above the tip-shaped SiGe source/drain regions.

4 more elements

Dependencies are inferred from the claim text.

Planar gate-insulated vacuum channel transistor

Life of this patent

Planar gate-insulated vacuum channel transistor

Life of this patent

Abstract

Claims14