Configurable interface alignment buffer between DRAM and logic unit for multiple-wafer image sensors

An image sensor comprising:

• an array of pixels configured to sense light and configured in a plurality of blocks;
• where each block of pixels is coupled to a separate analog-to-digital converter (ADC) adapted to provide digitized image data;
• the ADCs being coupled to feed digitized image data into an image RAM;
• and
• the image RAM is coupled to provide digitized image data to an alignment buffer in a first pixel order;
• where the array of pixels, the ADCs, and the image RAM are each physically located on a separate die, the separate die being interconnected by die-to-die bonds;
• where the alignment buffer is configured to provide digitized image data to an image processor in a second pixel order, the second pixel order different from the first pixel order;
• wherein the alignment buffer comprises a multiport RAM capable of being read at a first address and written at a second address simultaneously, the first address being different from the second address;
• and
• wherein the multiport RAM is configured to be written in words of a first length and to be read in words of a second length shorter than the first length.

A method of providing image data to an image processor in a multiple-stacked-wafer image sensor, the image sensor having a pixel sensor die having pixels organized as blocks of pixels, comprising:

• repetitively reading pixel data from a pixel in each block of pixels through an analog-to-digital converter (ADC) to generate digitized pixel data and simultaneously writing the digitized pixel data for the pixel in each block into an image RAM until all pixels in each block are read;
• reading the digitized pixel data from the image RAM located on a separate wafer from the ADC into an alignment buffer, the pixel data being in a first pixel order in the image RAM;
• and
• reading the digitized pixel data from the alignment buffer into an image processor in a second pixel order;
• the image processor the image processor being located on the same wafer as the ADCs and on a different wafer than the pixel array.