US 10,834,351 B2 · Bitline settling speed enhancement

Abstract

An image sensor includes pixel circuitry with a photodiode to receive light and output a pixel signal. The image sensor also includes readout circuitry with a first sample and hold transistor coupled to the pixel circuitry, and a first capacitor coupled to the first sample and hold transistor to receive the pixel signal. A second sample and hold transistor is coupled to the pixel circuitry, and a second capacitor is coupled to the second sample and hold transistor to receive the pixel signal. A first output switch is coupled to output the pixel signal from the first capacitor, and a second output switch is coupled to output the pixel signal from the second capacitor. A boost transistor is coupled to connect the first output switch and the second output switch when the boost transistor is turned on.

Claims20

Dependent claims

An image sensor, comprising:

pixel circuitry, including a photodiode disposed in an image wafer, to receive light and output a pixel signal;
and
readout circuitry, including:
a first sample and hold transistor coupled to the pixel circuitry;
a first capacitor coupled to the first sample and hold transistor to receive the pixel signal when the first sample and hold transistor is turned on;
a second sample and hold transistor coupled to the pixel circuitry;
a second capacitor coupled to the second sample and hold transistor to receive the pixel signal when the second sample and hold transistor is turned on;
a first output switch coupled to output the pixel signal from the first capacitor;
a second output switch coupled to output the pixel signal from the second capacitor;
and
a boost transistor coupled to connect the first output switch and the second output switch when the boost transistor is turned on.

8 more elements

An imaging system, comprising:

a plurality of photodiodes disposed in an imaging wafer and arranged into an array to receive image light, wherein each photodiode in the plurality of photodiodes is included in pixel circuitry to output a pixel signal;
readout circuitry disposed, at least in part, in a logic wafer coupled to the image wafer, the readout circuitry including:
a first sample and hold transistor coupled to the pixel circuitry;
a first capacitor coupled to the first sample and hold transistor to receive the pixel signal when the first sample and hold transistor is turned on;
a second sample and hold transistor coupled to the pixel circuitry
a second capacitor coupled to the second sample and hold transistor to receive the pixel signal when the second sample and hold transistor is turned on;
a first output switch coupled to output the pixel signal from the first capacitor;
a second output switch coupled to output the pixel signal from the second capacitor;
and
a boost transistor coupled to connect the first output switch and the second output switch when the boost transistor is turned on.

7 more elements

Dependencies are inferred from the claim text.

Bitline settling speed enhancement

Life of this patent

Bitline settling speed enhancement

Life of this patent

Abstract

Claims20