Low voltage differential signal transmitter, method for generating a low voltage differential signal, and data transmission device

A method for generating a low voltage differential signal, comprising:

• receiving a first clock signal;
• processing the first clock signal to obtain a second clock signal, reading a first data signal under drive of the second clock signal, and outputting a third clock signal and a second data signal;
• sampling the third clock signal and the second data signal according to the first clock signal;
• outputting a serial low voltage differential clock signal and a serial low voltage differential data signal;
• wherein, the second clock signal is obtained by attenuating a frequency of the first clock signal by a preset proportion;
• and the second data signal and the third clock signal are generated by operations of:
• matching an output speed of the first data signal with a speed of reading the first data signal and storing the first data signal;
• outputting an effective output signal with a high electric level when detecting that the first data signal is stored;
• and outputting the second data signal and the third clock signal in response to the effective output signal.

A data transmission device, comprising:

• a phase-locked loop configured to generate a first clock signal;
• a low voltage differential signal transmitter connected with the phase-locked loop and including a controller and a physical layer chip connected with each other;
• wherein, the controller is configured to receive the first clock signal, process the first clock signal to obtain a second clock signal, read a first data signal under drive of the second clock signal, and output a third clock signal and a second data signal;
• the physical layer chip is configured to receive the first clock signal and the signals output by the controller, sample the third clock signal and the second data signal according to the first clock signal, and output a serial low voltage differential clock signal and a serial low voltage differential data signal;
• and
• a receiver connected with the low voltage differential signal transmitter and configured to receive the serial low voltage differential data signal and the serial low voltage differential clock signal;
• wherein, the low voltage differential signal transmitter further comprises a digital logic circuit, the digital logic circuit includes a frequency divider, the frequency divider is configured to attenuate a frequency of the first clock signal by a preset proportion to obtain the second clock signal;
• the controller includes a buffer and a processor connected with each other, the buffer is connected with the digital logic circuit, and the buffer is configured to match an output speed of the first data signal with a speed of reading the first data signal by the controller and store the first data signal;
• the processor is configured to output an effective output signal with a high electric level to the digital logic circuit when detecting that the buffer stores the first data signal, such that the digital logic circuit outputs the second data signal and the third clock signal.