BISS protocol data decoding method and interface system

A method for Bidirectional Synchronous Serial (BISS) protocol data decoding, wherein the method is performed by an FPGA chip comprising an MA drive module, an SL receiving module and a CRC check module, and the method comprises:

• receiving, by the MA drive module, an enable signal en;
• transmitting, by the MA drive module, an MA clock signal to the SL receiving module;
• detecting a trigger signal of SL by the SL receiving module;
• reading SL data by the SL receiving module on detecting a start bit of the SL by the SL receiving module;
• transmitting, by the SL receiving module, a done signal to the MA drive module to stop operation of the MA drive module and transmitting, by the SL receiving module, a did signal to the CRC check module, after the SL data is read by the SL receiving module;
• performing, by the CRC check module, CRC check on the SL data after the did signal is received by the CRC check module;
• and
• outputting, by the CRC check module, a correct position value after the check is completed, wherein
• receiving by the MA drive module the enable signal en, transmitting by the MA drive module the MA clock signal to the SL receiving module, and detecting the trigger signal of the SL by the SL receiving module comprises:
• receiving, by the MA drive module, the enable signal en;
• transmitting, by the MA drive module, the MA clock signal to the SL receiving module;
• generating, by the SL receiving module, a maclk signal based on a time difference between the MA clock signal and an SL signal;
• and
• detecting, by the SL receiving module, the trigger signal of the SL by using a rising edge of the maclk signal.