Error trapping in memory structures
AssigneeInternational Business Machines Corporation
InventorsGlenn Gilda, Arthur O'Neill
Life of this patent
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Abstract
Embodiments include methods, systems and circuits for operating an error trapping logic circuit in a memory device. Aspects include receiving, during a first clock cycle, data and check bits for the data from a memory location and determining, during the first clock cycle, whether the data includes any error by calculating an error syndrome from the data and the check bits. Aspects also include determining, during a second clock cycle, a type of the error based on a full decoding of the error syndrome. Aspects further include determining whether to store the data, the check bits and the error syndrome in trap registers of the error trapping logic circuit based on an operating mode of the error trapping logic circuit and the type of the error.
Claims18
A computer-implemented method for operating an error trapping logic circuit in a memory device, the method comprising:
- receiving, during a first clock cycle, data and check bits for the data from a memory location;
- determining, during the first clock cycle, whether the data includes any error by calculating an error syndrome from the data and the check bits;
- determining, during a second clock cycle, a type of the error based on a full decoding of the error syndrome;
- determining whether to store the data, the check bits and the error syndrome in trap registers of the error trapping logic circuit based on an operating mode of the error trapping circuit and the type of the error;
- and
- preventing the data, the check bits and the error syndrome from being stored in trap registers based upon receiving a cancel signal, wherein the cancel signal is received after the second clock cycle.
A memory device comprising:
- a plurality of memory banks each comprising a plurality of memory sections configured to store data, each of the plurality of memory sections having an error trapping logic circuit that is configured to:
- receive, during a first clock cycle, data and check bits for the data from a memory location;
- determine, during the first clock cycle, whether the data includes any error by calculating an error syndrome from the data and the check bits;
- determine, during a second clock cycle, a type of the error based on a full decoding of the error syndrome;
- and
- determine whether to store the data, the check bits and the error syndrome in trap registers of the error trapping logic circuit based on an operating mode of the error trapping logic circuit and the type of the error;
- and
- prevent the data, the check bits and the error syndrome from being stored in trap registers based upon receiving a cancel signal, wherein the cancel signal is received after the second clock cycle.
An error trapping logic circuit that is configured to:
- receive, during a first clock cycle, data and check bits for the data from a memory location;
- determine, during the first clock cycle, whether the data includes any error by calculating an error syndrome from the data and the check bits;
- determine, during a second clock cycle, a type of the error based on a full decoding of the error syndrome;
- determine whether to store the data, the check bits and the error syndrome in trap registers of the error trapping logic circuit based on an operating mode of the error trapping logic circuit and the type of the error;
- and
- prevent the data, the check bits and the error syndrome from being stored in trap registers based upon receiving a cancel signal, wherein the cancel signal is received after the second clock cycle.
Dependencies are inferred from the claim text.