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US 10,833,694 B2Granted
Circuits and methods for time-delay to digital converters
AssigneeThe Trustees of Columbia University in the City of New York
InventorsDaniel De Godoy Peixoto, Xiaofan Jiang, Peter Kinget
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Abstract
In accordance with some embodiments, polarity-coincidence, adaptive time-delay estimation (PCC-ATDE), mixed-signal techniques are provided. In some embodiments, these techniques use 1-bit quantized signals and negative-feedback architectures to directly determine a time-delay between signals at analog inputs and convert the time-delay to a digital number.
Claims10
A circuit for a time-delay to digital converter, comprising:
- a first microphone having a first output;
- a second microphone having a second output;
- a first one-bit analog-to-digital converter having a first input coupled to the first output and having a third output;
- a second one-bit analog-to-digital converter having a second input coupled to the second output and having a fourth output;
- a first variable time delay having a third input coupled to the third output, a fourth input, and a fifth output, wherein the fourth input controls a delay amount of the first variable time delay;
- a second variable time delay having a fifth input coupled to the fourth output, a sixth input, and a sixth output, wherein the sixth input controls a delay amount of the second variable time delay;
- a first multiplier having a seventh input coupled to the fifth output, an eighth input coupled to the sixth output, and a seventh output;
- a third time delay having a ninth input coupled to the sixth output, and an eighth output;
- a second multiplier have a tenth input coupled to the fifth output, and an eleventh input coupled to the eighth output, and a ninth output;
- a subtractor having a twelfth input coupled to the seventh output, a thirteenth input coupled to the ninth output, and a tenth output;
- an accumulator having a fourteenth input coupled to the tenth output, and an eleventh output;
- an attenuator having a fifteenth input coupled to the eleventh output, and a twelfth output;
- a differential splitter having a sixteenth input coupled to the twelfth output, a thirteenth output, and a fourteenth output;
- a first adder having a seventeenth input coupled to the thirteenth output, an eighteenth input coupled to an offset signal, and a fifteenth output coupled to the sixth input;
- and
- a second adder having a nineteenth input coupled to the fourteenth output, a twentieth input coupled to the offset signal, and a sixteenth output coupled to the fourth input.
13 more elements
Dependencies are inferred from the claim text.