Time-interleaved analog-to-digital converter system

A time-interleaved analog-to-digital converter (ADC) system, comprising;

• an input port configured to receive an analog signal;
• an ADC-array comprising M ADCs arranged in parallel, each ADC being configured to receive and to convert a portion of the analog signal into a digital signal at a sample rate fs;
• where M≥2;
• a sample clock module having a sampling frequency fs=F/M, F being a system clock, wherein consecutive sampling events for the ADCs are delayed by tD=1/(fs*M);
• a first multiplexer connected to each of the ADCs and configured to concatenate output signals from the ADCs into a single data stream;
• a reference ADC configured to receive and to convert the analog signal into a digital reference signal at an average sampling rate fref lower than fs, wherein each sampling instant of the reference ADC corresponds to a sampling instant of an ADC in the array of ADCs, and wherein the ADC to select for each reference ADC sampling instant is randomized over time;
• and
• a reference ADC clock control module configured to control the sampling instants of the reference ADC;
• a correction module connected to the first multiplexer to receive the data stream, the correction module comprising M correction blocks, each correction block being configured to correct a portion of the data stream AD-converted by a corresponding ADC, wherein an output signal from the reference ADC is provided to the error correction block configured to correct the portion of the data stream from the ADC from which the reference ADC sampling instant is selected;
• and
• a second multiplexer connected to an output of each of the correction blocks and configured to combine output signals from each of the error correction blocks to provide an ADC-system output signal.

A method for analog-to-digital (AD) conversion in a system comprising a time-interleaved analog-to-digital converter (ADC) having an ADC-array comprising M, ADCs arranged in parallel, where M≥2, the method comprising:

• receiving an analog signal;
• AD-converting the signal by means of the ADC-array using a sampling rate fs;
• in a reference ADC, converting the analog signal into a digital reference signal at an average sampling rate fref lower than fs, wherein each sampling instant of the reference ADC corresponds to a sampling instant of an ADC in the array of ADCs, and wherein the ADC to select for each reference ADC sampling instant is randomized over time;
• adjusting the digital signal outputs of the array of ADCs into a corrected digital output signal based on samples of the digital reference signal and the digital signals from the corresponding selected ADCs;
• and
• selecting the ADC to sample based on an offset time toffset=D/(fs*M) added to the fundamental period 1/fs, such that the period between two consecutive sample events for the reference ADC is 1/fs+D/(fs*M), where D is a random integer D=0 . . . (M−1).

A time-interleaved analog-to-digital converter (ADC) module, comprising:

• an input port for to receiving an analog signal;
• an ADC-array module for analog-to-digital conversion of the signal at a sampling rate fs;
• the ADC-array module comprising an array of M ADCs;
• a reference ADC module for converting the analog signal into a digital reference signal at an average sampling rate fref lower than fs, wherein each sampling instant of the reference ADC corresponds to a sampling instant of an ADC in the array of ADCs, and wherein the ADC to select for each reference ADC sampling instant is randomized over time;
• and
• a correction module for adjusting the digital signal outputs of the array of ADCs into a corrected digital output signal based on samples of the digital reference signal and the digital signals from the corresponding selected ADCs;
• and
• a reference ADC clock control module configured to:
• control the sampling instants of the reference ADC;
• select the ADC to sample based on an offset time toffset=D/(fs*M) added to the fundamental period 1/fs, such that the period between two consecutive sample events for the reference ADC is 1/fs+D/(fs*M), where D is a random integer D=0 . . . (M−1).