Method and circuits for reducing noise in phase-locked loops

A phase lock loop (PLL) device configured to receive a reference input signal;

• and generate an output signal, the PLL device comprising:
• a phase frequency detector configured to:
• receive the reference input signal and a feedback signal;
• and
• generate one or more comparison signals indicating whether the reference input signal is leading the feedback signal or whether the feedback signal is leading the reference input signal;
• a charge pump coupled to the phase frequency detector and configured to:
• receive the one or more comparison signals;
• and
• convert the one or more comparison signals into a driving current;
• a loop filter coupled to the charge pump and configured to:
• receive the driving current from the charge pump;
• and
• split the driving current to generate a first voltage signal and a second voltage signal;
• and
• a voltage controlled oscillator coupled to the loop filter and configured to:
• receive the first voltage signal and generate a first control current;
• receive the second voltage signal and generate a second control current;
• and
• combine the first control current and the second control current to jointly drive a charge controlled oscillator such that the output signal of a desired frequency is generated.