Calibration of an interpolative divider using a virtual phase-locked loop

A method comprising:

• generating an output clock signal using an interpolative divider responsive to a clock signal, a control code, and a phase interpolator calibration signal;
• and
• generating the phase interpolator calibration signal based on the clock signal, the output clock signal, and a phase interpolator code, wherein
• generating the phase interpolator calibration signal comprises:
• generating a digital phase error signal based on a reference timestamp signal and a timestamp signal based on the clock signal and the output clock signal;
• and
• adapting the phase interpolator calibration signal based on the digital phase error signal.

A method comprising:

• generating an output clock signal based on a clock signal, a control code, and a phase interpolator calibration signal;
• generating a digital error signal based on a downsampled version of the output clock signal and an estimated version of the downsampled version of the output clock signal;
• and
• generating the phase interpolator calibration signal based on the digital error signal and a phase interpolator control code using a least mean squares filter.