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US 10,833,681 B1Granted
Data recovery technique for time interleaved receiver in presence of transmitter pulse width distortion
AssigneeNVIDIA Corporation
InventorsGaurawa Kumar, Ky-Anh Tran, Olakanmi Oluwole, Vishnu Balan
Life of this patent
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Abstract
This disclosure relates to a receiver comprising a clock and data recovery loop and a phase offset loop. The clock and data recovery loop may be controlled by a sum of gradients for a plurality of data interleaves. The phase offset loop may be controlled by an accumulated differential gradient for each of the data interleaves.
Claims27
A receiver comprising:
- a clock and data recovery loop controlled by a sum of gradients for a plurality of data interleaves;
- a phase offset loop controlled by an accumulated differential gradient for each of the plurality of data interleaves;
- a phase detector configured to determine the sum of gradients;
- and
- a multiphase clock generator configured to receive the sum of gradients from the phase detector.
2 more elements
A clock and data recovery circuit comprising:
- a phase detector configured to determine an accumulated differential gradient for each of a plurality of data signals and to determine a sum of gradients of the data signals;
- a multiphase clock generator coupled to receive the sum of gradients from the phase detector;
- and
- a plurality of configurable delay elements each configured to receive one of the accumulated differential gradients.
1 more element
A clock and data recovery circuit comprising:
- a plurality of sample and hold elements controlled by delay circuits;
- a phase detector configured to output a plurality of accumulated differential gradients for data signals from the plurality of sample and hold elements to control the delay circuits;
- and
- a multiphase clock generator supplying clock signals to the delay circuits, the multiphase clock generator controlled by a sum of gradients for the data signals.
1 more element
A method for controlling a data slicer, the method comprising:
- sampling each of a plurality of data signals at a different time by applying a delayed multiphase clock signal to each of the data signals via a different delay circuit;
- configuring each of the different delay circuits with an accumulated differential gradient for a different one of the data signals;
- supplying each of the different delay circuits with a different one of a plurality of outputs of a multiphase clock;
- and
- controlling the multiphase clock with a sum of gradients of the data signals.
2 more elements
A receiver comprising:
- a clock and data recovery loop controlled by a sum of gradients for a plurality of data interleaves;
- a phase offset loop controlled by an accumulated differential gradient for each of the plurality of data interleaves;
- a phase detector configured to determine the accumulated differential gradient for each of the data interleaves;
- and
- a plurality of delay elements each coupled to receive the accumulated differential gradient for one of the data interleaves from the phase detector.
2 more elements
Dependencies are inferred from the claim text.