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US 10,833,678 B1Granted
Performance CMOS voltage level-up shifter circuit topology using pre-drive pull-up transistors
AssigneeHewlett Packard Enterprise Development LP
InventorPaul Armstrong
Life of this patent
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Abstract
In a first example a voltage level-shifting device includes a level-shifting stage circuit. The level-shifting stage circuit includes a first level-shifting inverter circuit to invert a buffered input signal to drive a first internal node, a second level-shifting inverter circuit to invert a buffered inverted input signal to drive a second internal node, a first pre-drive circuit that receives the buffered inverted input signal, and drives the second internal node based on the state of the buffered inverted input signal, and a second pre-drive circuit that receives the buffered input signal, and drives the first internal node based on the state of the buffered input signal.
Claims13
A voltage level-shifting device, comprising:
- a level-shifting stage circuit including:
- a first level-shifting inverter circuit to invert a buffered input signal to drive a first internal node;
- a second level-shifting inverter circuit to invert a buffered inverted input signal to drive a second internal node, the buffered inverted input signal having a logically opposite state of the buffered input signal;
- a first pre-drive circuit that receives the buffered inverted input signal, and drives the second internal node based on a state of the buffered inverted input signal;
- and
- a second pre-drive circuit that receives the buffered input signal, and drives the first internal node based on a state of the buffered input signal;
- and
- an input stage circuit to produce the buffered input signal and the buffered inverted input signal from a received input signal;
- wherein:
- the input stage circuit and level-shifting stage circuit use a shared power ground;
- the input stage circuit is powered by a first power supply;
- and
- the level-shifting stage circuit is powered by a second power supply, the second power supply having a greater voltage than the first power supply;
- the input stage circuit and level-shifting stage circuit use a shared power ground;
- the input stage circuit is powered by a first power supply;
- the level-shifting stage circuit is powered by a second power supply, the second power supply having a greater voltage than the first power supply
- the first pre-drive circuit includes a first P-type Metal-Oxide-Semiconductor (“PMOS”) transistor and a second PMOS transistor;
- a first power node of the first PMOS transistor is electrically connected to the second power supply;
- a second power node of the first PMOS transistor is electrically connected to a first power node of the second PMOS transistor;
- a control node of the first PMOS transistor is electrically connected to a buffered inverted input node that provides the buffered inverted input signal;
- and
- a control node and a second power node of the second PMOS transistor are electrically connected to the second internal node.
19 more elements
A voltage level-shifting device, comprising:
- a Complementary Metal-Oxide-Semiconductor (“CMOS”) input stage circuit to produce a buffered input signal and a buffered inverted input signal based on a received input signal, the buffered inverted input signal having a logically opposite state of the buffered input signal;
- and
- a level-shifting stage circuit that includes:
- a first level-shifting inverter circuit to invert the buffered input signal to drive a first internal node;
- a second level-shifting inverter circuit to invert the buffered inverted input signal to drive a second internal node;
- a first pre-drive circuit that receives the buffered inverted input signal, and drives the second internal node based on a state of the buffered inverted input signal;
- and
- a second pre-drive circuit that receives the buffered input signal, and drives the first internal node based on a state of the buffered input signal;
- wherein:
- the first pre-drive circuit includes a first P-type Metal-Oxide-Semiconductor (“PMOS”) transistor having a first power node connected to a power supply and a control node electrically connected to a buffered inverted input node that provides the buffered inverted input signal;
- the first PMOS transistor turns on to supply current to the second internal node in response to the buffered inverted input signal transitioning from a high state to a low state;
- the first pre-drive circuit further includes a second PMOS transistor having a first power node connected to a second node of the first PMOS transistor, and a second power node connected to the second internal node;
- and
- the second PMOS transistor is configured to turn off in response to the second internal node transitioning to a high state.
11 more elements
Dependencies are inferred from the claim text.