Low power logic family

A logic gate consisting of enhancement mode MOS transistors implementing Boolean function with at least two inputs, characterized in

• the first branch is realized by a single transistor with gate and source terminals connected to the output of the logic gate, and drain terminal to a first voltage;
• at least one second branch, the branches realizing the opposite logic operation to the first branch, where the at least one second branch consists of at least two serially connected transistors having different independent inputs associated with their gate terminals, wherein drain terminal of the serially connected transistors is connected to the output of the logic gate and source terminal of the serially connected transistors is connected to a second voltage, wherein the transistors in the first branch and the at least one second branch are having different aspect ratios;
• the first branch pulls the output close to any one of the first voltage and the second voltage when no second branch is in conductive mode, and the first branch pulls the output close to any one of the first voltage and the second voltage, when second branch is in conductive mode;
• all the transistors forming the logic gate have the same substrate voltage, wherein the substrate voltage of the transistors forming the gate is externally adjustable to control the switching speed of the logic gate.