Semiconductor device

An operation adjustment method for a semiconductor device comprising:

• a semiconductor substrate;
• a deep P-well formed in the semiconductor substrate;
• an N-well formed in the deep P-well;
• a P-well formed in the deep P-well;
• a semiconductor layer formed in a surface portion of the semiconductor substrate;
• and a buried dielectric layer formed between the semiconductor layer and the deep P-well to electrically isolate the semiconductor layer and the deep P-well, a pn junction being formed between the N-well and the P-well, a PMOS transistor being formed in the semiconductor layer at a position opposing to the N-well, an NMOS transistor being formed in the semiconductor layer at a position opposing to the P-well, the method comprising:
• (a) obtaining a drain current-substrate bias voltage characteristic of the PMOS transistor for a source-gate voltage of 0V;
• (b) obtaining a highest substrate bias voltage which turns on the PMOS transistor from the drain current-substrate bias voltage characteristic;
• (c) determining a lower limit of a substrate bias voltage of the NMOS transistor as a voltage obtained by adding a built-in potential of the pn junction to the highest substrate bias voltage;
• and
• (d) determining the substrate bias voltage of the NMOS transistor as a negative voltage higher than the lower limit.

A semiconductor device, comprising:

• a main circuit comprising a PMOS transistor and an NMOS transistor;
• a substrate bias voltage generator circuit configured to generate a substrate bias voltage of the PMOS transistor;
• and
• a control circuit configured to control the substrate bias voltage of the PMOS transistor,
• wherein the main circuit comprises:
• a deep N-well formed in a semiconductor substrate;
• an N-well formed in the deep N-well;
• a P-well formed in the deep N-well;
• a semiconductor layer formed in a surface portion of the semiconductor substrate;
• and
• a buried dielectric layer formed between the semiconductor layer and the deep N-well to electrically isolate the semiconductor layer from the deep N-well,
• wherein a pn junction is formed between the N-well and the P-well,
• wherein the PMOS transistor is formed in the semiconductor layer at a position opposing to the N-well,
• wherein the NMOS transistor is formed in the semiconductor layer at a position opposing to the P-well,
• wherein the control circuit is configured to set a substrate bias voltage of the PMOS transistor to a first voltage when the semiconductor device is placed in a first mode,
• wherein the control circuit is configured to set the substrate bias voltage of the PMOS transistor to a second voltage higher than the first voltage when the semiconductor device is placed in a second mode, and
• wherein the second voltage is a positive voltage lower than a voltage obtained by subtracting a built-in potential of the pn junction from a lowest substrate bias voltage which turns on the NMOS transistor when a source-gate voltage thereof is 0V.

A semiconductor device, comprising:

• a main circuit comprising a PMOS transistor and an NMOS transistor;
• a substrate bias voltage generator circuit configured to generate a substrate bias voltage of the NMOS transistor;
• and
• a control circuit configured to control the substrate bias voltage of the NMOS transistor,
• wherein the main circuit comprises:
• a deep P-well formed in a semiconductor substrate;
• an N-well formed in the deep P-well;
• a P-well formed in the deep P-well;
• a semiconductor layer formed in a surface portion of the semiconductor substrate;
• and
• a buried dielectric layer formed between the semiconductor layer and the deep P-well to electrically isolate the semiconductor layer from the deep P-well,
• wherein a pn junction is formed between the N-well and the P-well,
• wherein the PMOS transistor is formed in the semiconductor layer at a position opposing to the N-well,
• wherein the NMOS transistor is formed in the semiconductor layer at a position opposing to the P-well,
• wherein the control circuit is configured to set a substrate bias voltage of the NMOS transistor to a first voltage when the semiconductor device is placed in a first mode,
• wherein the control circuit is configured to set the substrate bias voltage of the NMOS transistor to a second voltage lower than the first voltage when the semiconductor device is placed in a second mode, and
• wherein the second voltage is a negative voltage higher than a voltage obtained by adding a built-in potential of the pn junction to a highest substrate bias voltage which turns on the PMOS transistor when a source-gate voltage thereof is 0V.