Driving circuit for high-side transistor, switching circuit, and controller for DC/DC converter

A driving circuit for an N-channel or NPN-type high-side transistor, the driving circuit comprising:

• a level shift circuit configured to level-shift an input signal;
• and
• a buffer configured to drive the N-channel or NPN-type high-side transistor according to an output of the level shift circuit,
• wherein the level shift circuit includes:
• a differential conversion circuit of an open drain type configured to convert the input signal into a differential signal;
• a latch circuit configured to perform a state transition with a differential output of the differential conversion circuit as a trigger;
• and an assist circuit configured to inject an assist current into the latch circuit in synchronization with the input signal, and
• wherein the latch circuit includes:
• a P-channel ninth transistor and a P-channel tenth transistor whose sources are each connected to a bootstrap line and whose gates and drains are each cross-coupled;
• a high breakdown voltage eleventh transistor whose gate is connected to a switching line and whose source is connected to the drain of the P-channel ninth transistor;
• and
• a high breakdown voltage twelfth transistor whose gate is connected to the switching line and whose source is connected to the drain of the P-channel tenth transistor.

A controller for a DC/DC converter, the controller comprising:

• a pulse modulator configured to generate a pulse signal such that an output of the DC/DC converter approaches a target value;
• and
• a driving circuit configured to drive an N-channel or NPN-type high-side transistor based on the pulse signal,
• wherein the driving circuit includes:
• a level shift circuit configured to level-shift the pulse signal;
• and
• a buffer configured to drive the N-channel or NPN-type high-side transistor according to an output of the level shift circuit,
• wherein the level shift circuit includes:
• a differential conversion circuit of an open drain type configured to convert the pulse signal into a differential signal;
• a latch circuit configured to perform a state transition with a differential output of the differential conversion circuit as a trigger;
• and
• an assist circuit configured to accelerate the state transition by injecting an assist current into the latch circuit in synchronization with the pulse signal, and
• wherein the assist circuit includes:
• a pulse generator configured to generate a first pulse signal asserted for a predetermined time from a positive edge of an input signal and a second pulse signal asserted for the predetermined time from a negative edge of the input signal;
• an N-channel first transistor configured to receive the first pulse signal at a gate of the N-channel first transistor;
• a first current mirror circuit connected to a bootstrap line and configured to turn back a current of the N-channel first transistor;
• an N-channel second transistor configured to receive the second pulse signal at a gate of the N-channel second transistor;
• and
• a second current mirror circuit connected to the bootstrap line and configured to turn back a current of the N-channel second transistor.

A controller for a DC/DC converter, the controller comprising:

• a pulse modulator configured to generate a pulse signal such that an output of the DC/DC converter approaches a target value;
• and
• a driving circuit configured to drive an N-channel or NPN-type high-side transistor based on the pulse signal,
• wherein the driving circuit includes:
• a level shift circuit configured to level-shift the pulse signal;
• and
• a buffer configured to drive the N-channel or NPN-type high-side transistor according to an output of the level shift circuit,
• wherein the level shift circuit includes:
• a differential conversion circuit of an open drain type configured to convert the pulse signal into a differential signal;
• a latch circuit configured to perform a state transition with a differential output of the differential conversion circuit as a trigger;
• and
• an assist circuit configured to accelerate the state transition by injecting an assist current into the latch circuit in synchronization with the pulse signal, and
• wherein the latch circuit includes:
• a P-channel ninth transistor and a P-channel tenth transistor whose sources are each connected to a bootstrap line and whose gates and drains are each cross-coupled;
• a high breakdown voltage eleventh transistor whose gate is connected to a switching line and whose source is connected to the drain of the P-channel ninth transistor;
• and
• a high breakdown voltage twelfth transistor whose gate is connected to the switching line and whose source is connected to the drain of the P-channel tenth transistor.