Phase error correction for clock signals
AssigneeTexas Instruments Incorporated
InventorJianfeng Jiang
Life of this patent
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Abstract
A multi-phase clock generator circuit includes a phase reference generator circuit configured to generate a phase reference signal in response to a phase selection signal and a peak ramp signal. A phase error correction circuit is configured to provide an error signal based on a synchronization clock signal and a multi-phase clock signal. The error signal is applied to the phase reference signal to correct for phase errors in the multi-phase clock signal. A comparator is configured to compare a ramp signal and the phase reference signal to produce the multi-phase clock signal.
Claims24
A multi-phase clock generator circuit comprising:
- a phase reference generator circuit configured to generate a phase reference signal in response to a phase selection signal and a peak ramp signal;
- a phase error correction circuit configured to provide an error signal based on a synchronization clock signal and a multi-phase clock signal, the error signal being applied to the phase reference signal to correct for phase errors in the multi-phase clock signal and produce a corrected phase reference signal;
- and
- a comparator configured to compare a ramp signal and the corrected phase reference signal to produce the multi-phase clock signal.
A multi-phase clock generator circuit comprising:
- a ramp generator that includes an output;
- a comparator having first and second inputs and a clock output, the first input being coupled to the output of the ramp generator;
- a peak detector circuit having an input coupled to the output of the ramp generator;
- a buffer having an input coupled to an output of the peak detector circuit;
- a phase reference generator circuit having an input coupled to an output of the buffer and having an output coupled to the second input of the comparator;
- and
- a phase error correction circuit having an input coupled to the clock output and having an output coupled to the second input of the comparator.
A system comprising:
- a ramp generator configured to provide ramp signal based on a synchronization clock signal;
- a peak detector configured to detect a peak in the ramp signal during each period of a multi-phase clock signal and provide a peak ramp signal;
- a phase reference generator configured to generate a phase reference signal based on the peak ramp signal and a phase angle selection signal;
- a phase error correction circuit configured to provide an error current signal based on the synchronization clock signal and the multi-phase clock signal, the error current signal being applied to the phase reference generator to correct the phase reference signal and provide a corrected phase reference signal;
- a comparator configured to provide the multi-phase clock signal based on the ramp signal and the corrected phase reference signal;
- and
- a power supply configured to supply power at an output thereof based on the multi-phase clock signal.
Dependencies are inferred from the claim text.