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US 10,833,662 B2Granted
Delay cell and delay line having the same
AssigneeSK hynix Inc.
InventorsJa-Young Kim, Hyun-Ju Ham
Life of this patent
Estimating the term…
Abstract
A delay cell includes: a plurality of delay elements coupled in series; and at least one three-phase inverter that is coupled in parallel to at least one of the delay elements, and that receives through a first control terminal a first bias voltage for compensating for a variation of a power source voltage, and receives through a second control terminal a second bias voltage for compensating for a variation of a ground voltage.
Claims22
A delay cell comprising:
- a plurality of delay elements coupled in series;
- and
- at least one three-phase inverter that is coupled in parallel with at least one of the delay elements, and that receives through a first control terminal a first bias voltage for moving in a direction opposite to the variation of a power source voltage to compensate for a variation of the power source voltage, and receives through a second control terminal a second bias voltage for moving in a direction opposite to the variation of a ground voltage to compensate for a variation of the ground voltage.
A delay line comprising:
- a plurality of first delay elements coupled in series and suitable for receiving an input signal based on a plurality of delay control signals;
- a plurality of second delay elements coupled in series and suitable for outputting an output signal;
- a plurality of third delay elements suitable for coupling the first delay elements and the second delay elements to each other based on the delay control signals;
- and
- a plurality of first three-phase inverters that are coupled in parallel with the first delay elements, and that receive through first control terminals a plurality of first bias voltages for compensating for a variation of a power source voltage, and receive through second control terminals a plurality of second bias voltages for compensating for a variation of a ground voltage.
2 more elements
A delay locked loop circuit comprising:
- a delay line suitable for selecting unit delays to be used based on a plurality of delay control signals, delaying an external clock, and outputting a delay clock, and controlling a driving force of the unit delays based on a first bias voltage and a second bias voltage, wherein each of the unit delays includes a delay element and a three-phase inverter coupled in parallel with the delay element and operable based on the first and second bias voltages;
- a replica delayer suitable for receiving the delay clock and generating a feedback clock by reflecting a delay amount of an actual clock path;
- a phase detector suitable for generating a phase comparison signal by comparing a phase of the external clock and a phase of the feedback clock with each other;
- and
- a delay controller suitable for generating the delay control signals based on the phase comparison signal, and generating the first bias voltage that moves in a direction opposite to the variation of a power source voltage to compensate for a variation of the power source voltage and generating the second bias voltage that moves in a direction opposite to the variation of a ground voltage to compensate for a variation of the ground voltage, based on the delay control signals.
2 more elements
A delay cell comprising:
- a first voltage generator configured to generate a first bias voltage moving in a direction opposite to the variation of a first source voltage to compensate for variation in the first source voltage;
- a second voltage generator configured to generate a second bias voltage moving in a direction opposite to the variation of a second source voltage to compensate for variation in the second source voltage;
- a delay element operable based on the first and second source voltages;
- and
- a three-phase inverter coupled in parallel with the delay element and operable based on the first and second bias voltages.
2 more elements
A delay line comprising:
- a first voltage generator configured to generate a first bias voltage moving in a direction opposite to the variation of a first source voltage to compensate for variation in the first source voltage;
- a second voltage generator configured to generate a second bias voltage moving in a direction opposite to the variation of a second source voltage to compensate for variation in the second source voltage;
- and
- plural delay cells coupled to one another,
- wherein at least one delay cell among the delay cells includes:
- a delay element operable based on the first and second source voltages;
- and
- a three-phase inverter coupled in parallel with the delay element and operable based on the first and second bias voltages.
5 more elements
A delay locked loop circuit comprising:
- a control circuit configured to generate a first bias voltage moving in a direction opposite to the variation of a first source voltage to compensate for variation in the first source voltage, and a second bias voltage moving in a direction opposite to the variation of a second source voltage to compensate for variation in the second source voltage, based on an external clock and a delay clock;
- and
- a delay line including at least one delay cell and configured to delay the external clock to generate the delay clock,
- wherein the delay cell includes:
- a delay element operable based on the first and second source voltages;
- and
- a three-phase inverter coupled in parallel with the delay element and operable based on the first and second bias voltages.
4 more elements
Dependencies are inferred from the claim text.