Ring oscillator, controlling circuit and methods for realignment

A ring oscillator, comprising:

• a controlling circuit, comprising:
• a pseudo pass-gate inverter formed by a first transistor and a second transistor coupled in series between a first power source and a second power source;
• a third transistor coupled between the first transistor and the first power source, wherein a gate of the third transistor is utilized to receive a realignment signal;
• and
• a fourth transistor coupled between an output of the pseudo pass-gate inverter and the second power source, having a gate coupled to the gate of the third transistor, wherein the first and fourth transistors are of a first conductive type, and the second and third transistors are of a second conductive type;
• and
• a delay chain, comprising a plurality of delay cells connected in series, wherein an input of the delay chain is connected to the output of the pseudo pass-gate inverter, wherein the input of the delay chain is directly connected to a drain of the first transistor, wherein each of the delay cells comprises:
• an inverter coupled between the first and second power sources;
• and
• a dummy transistor coupled between the inverter and the first power source, having a gate directly coupled to the second voltage source,
• wherein when the realignment signal is in a realignment state, the third transistor is turned off and the fourth transistor is turned on, and a waveform of drain of the fourth transistor is pulled to a first logic level from a second logic level in order to align a phase of the waveform of the ring oscillator,
• wherein a realignment gap is used to indicate a period when the realignment signal is in the realignment state, and a half period with the second logic level of the waveform is extended which is overlapped with the realignment gap.

A method for realigning a ring oscillator which comprises a pseudo pass-gate inverter, a first transistor, a second transistor and a delay chain, the method comprising:

• turning off the first transistor and turning on the second transistor when a realignment signal is in a realignment state, wherein the first transistor is coupled between the pseudo pass-gate inverter and a first power source, and the second transistor is coupled between an output of the pseudo pass-gate inverter and a second power source;
• turning off the second transistor and turning on the first transistor when the realignment signal is in a normal state;
• and
• converting a waveform of a drain of the second transistor from a second logic level to a first logic level in order to align a phase of the waveform of the ring oscillator when the realignment signal is in the realignment state, wherein an input of the delay chain is directly connected to output of the pseudo pass-gate inverter;
• and
• reducing a half period with the first logic level of the waveform which is overlapped with a realignment gap in the realignment state.