US 10,833,643 B1Granted

Method and structure for controlling bandwidth and peaking over gain in a variable gain amplifier (VGA)

AssigneeInphi Corporation

InventorTom Peter Edward Broekaert

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Abstract

A method of controlling bandwidth and peaking over gain in a variable gain amplifier (VGA) device and structure therefor. The device includes at least three differential transistor pairs configured as a cross-coupled differential amplifier with differential input nodes, differential bias nodes, differential output nodes, a current source node, and two cross-coupling nodes. The cross-coupled differential amplifier includes a load resistor coupled to each of the differential output nodes and one of the cross-coupling nodes, and a load inductor coupled to the each of the cross-coupling nodes and a power supply rail. A current source is electrically coupled to the current source node. The cross-coupling configuration with the load resistance and inductance results in a lower bandwidth and lowered peaking at low gain compared to high gain. Further, the tap point into the inductor can be chosen as another variable to “tune” the bandwidth and peaking in a communication system.

Claims18

Dependent claims

A variable gain amplifier (VGA) device comprising:

a differential input signal having a first input signal and a second input signal;
a differential bias signal having a first bias signal and a second bias signal;
a first differential transistor pair with transistors T1 and T2, wherein each transistor includes a first node, a second node, and a third node;
wherein the third nodes of each transistor in the pair are electrically coupled together;
a first load resistor electrically coupled to the second node of T2 and a first load node;
a first load inductor electrically coupled to the first load node and a power supply rail;
a second differential transistor pair with transistors T3 and T4, wherein each transistor includes a first node, a second node, and a third node;
wherein the third nodes of each transistor in the pair are electrically coupled together;
a second load resistor electrically coupled to the second node of T3 and a second load node;
a second load inductor electrically coupled to the second load node and the power supply rail;
wherein the second node of T4 is electrically coupled to the first load node;
wherein the second node of T1 is electrically coupled to the second load node;
wherein the second node of T2 and the second node of T3 form differential output nodes;
wherein the first node of T2 is electrically coupled to the first node of T3;
wherein the first bias signal is electrically coupled to the first node of T2 and the first node of T3;
wherein the first node of T1 is electrically coupled to the first node of T4;
wherein the second bias signal is electrically coupled to the first node of T1 and the first node of T4;
a third differential transistor pair with transistors T5 and T6, wherein each transistor includes a first node, a second node, and a third node;
wherein the third nodes of each transistor in the pair are electrically coupled to a current source node;
wherein the first input signal is electrically coupled to the first node of T5 and the second input signal is electrically coupled to the first node of T6;
and
a current source electrically coupled between the current source node and ground.

19 more elements

A variable gain amplifier (VGA) device comprising:

a differential input signal;
a differential bias signal;
a cross-coupled differential amplifier configured as a Gilbert cell having differential input nodes, differential bias nodes, differential output nodes, a current source node, and two cross-coupling nodes;
wherein the cross-coupled differential amplifier receives the differential input signal at the differential input nodes and includes first and second transistors, and the first and second transistors receives the differential bias signal at the differential bias nodes;
a first isolation resistor electrically coupled between the first transistor and a first one of the cross-coupling nodes;
and
a second isolation resistor electrically coupled between the second transistor and a second one of the cross-coupling nodes,
wherein the cross-coupled differential amplifier includes first and second load resistors each coupled to each of the differential output nodes and one of the cross-coupling nodes;
wherein the cross-coupled differential amplifier includes first and second load inductors each coupled to the each of the cross-coupling nodes and a power supply rail;
and
a current source electrically coupled to the current source node.

8 more elements

A method of controlling bandwidth and peaking over gain in a variable gain amplifier (VGA) device, the method comprising:

providing a cross-coupled differential amplifier configured as a Gilbert cell having differential input nodes, differential bias nodes, differential output nodes, a current source node, and two cross-coupling nodes;
wherein the cross-coupled differential amplifier includes first and second load resistors each coupled to each of the differential output nodes and one of the cross-coupling nodes;
wherein the cross-coupled differential amplifier includes first and second load inductors each coupled to the each of the cross-coupling nodes and a power supply rail;
providing a current source electrically coupled to the current source node;
providing a differential bias signal to the differential bias nodes;
providing a differential input signal to the differential input nodes;
and
amplifying, by the cross-coupled differential amplifier, the differential input signal at the differential output nodes, wherein the output of the cross-coupled differential amplifier is characterized by increased bandwidth and reduced peaking at low gain;
and
wherein the first load inductor includes a first tunable tap point and wherein the second load inductor includes a second tunable tap point and further comprising tuning, by the first and second tunable tap points, the load inductors to mitigate effects on bandwidth and peaking.

7 more elements

Dependencies are inferred from the claim text.