Methods and apparatus for an amplifier circuit

A method for removing an offset voltage from an output signal of an operational amplifier, comprising:

• generating:
• a first clock signal having a first phase;
• a second clock signal having a second phase;
• a third clock signal having a third phase;
• and
• a fourth clock signal having a fourth phase, according to a reference clock signal;
• selectively transmitting a first input signal and a second input signal to an input stage circuit with a first cross-connect circuit, wherein the first cross-connect circuit comprises:
• a first switch responsive to the first clock signal;
• a second switch in parallel with the first switch and responsive to the third clock signal;
• a third switch in series with the first switch and responsive to the third clock signal;
• and
• a fourth switch in series with the second switch and responsive to the first clock signal;
• selectively transmitting the first input signal and the second input signal from the input stage circuit to an output stage circuit with a second cross-connect circuit, wherein the second cross-connect circuit comprises:
• a fifth switch responsive to the second clock signal;
• a sixth switch in parallel with the fifth switch and responsive to the fourth clock signal;
• a seventh switch in series with the fifth switch and responsive to the fourth clock signal;
• and
• an eighth switch in series with the sixth switch and responsive to the second clock signal;
• and
• regulating a voltage of the input stage circuit with a voltage adjustment circuit.

A system, comprising:

• a clock generator configured to generate:
• a first clock signal having a first phase, a second clock signal having a second phase, a third clock signal having a third phase, and a fourth clock signal having a fourth phase, according to a reference clock signal;
• wherein the first, second, third, and fourth clock signals are distinct from each other;
• an operational amplifier in communication with the clock generator and comprising:
• a first cross-connect circuit responsive to the first clock signal and the third clock signal and configured to receive a first input signal and a second input signal;
• an input stage circuit connected to the first cross-connect circuit and configured to apply a first gain to the first and second input signals;
• a second cross-connect circuit connected to the input stage circuit and responsive to the second clock signal and the fourth clock signal;
• an output stage circuit connected to the second cross-connect circuit and configured to apply a second gain to the first and second input signals and generate an output voltage;
• and
• an analog-to-digital converter (ADC) configured to:
• operate according to an ADC clock;
• and
• convert the output voltage to a digital signal.