Buffer circuit, clock dividing circuit including the buffer circuit, and semiconductor device including the buffer circuit

A buffer circuit comprising:

• an amplifying circuit configured to change, based on a first input signal and a second input signal, voltage levels of a first output node and a second output node in a range between a first power voltage and a second power voltage;
• a latch circuit configured to latch the voltage levels of the first output node and the second output node;
• a first variable load coupled between a first power voltage terminal at the first power voltage and the first output node, wherein a resistance value of the first variable load varies based on a reset signal;
• a second variable load coupled between the first power voltage terminal and the second output node, wherein a resistance value of the second variable load varies based on the reset signal;
• and
• a reset circuit configured to drive the first output node to the second power voltage based on the reset signal.

A buffer circuit comprising:

• an amplifying circuit configured to change, based on a first input signal and a second input signal, voltage levels of a first output node and a second output node in a range between a first power voltage and a second power voltage;
• a latch circuit configured to latch the voltage levels of the first output node and the second output node;
• a first variable load configured to adjust, based on a first reset signal and a second reset signal, an amount of current provided by a first power voltage terminal at the first power voltage to the first output node;
• a second variable load configured to adjust, based on the first reset signal and a third reset signal, an amount of current provided by the first power voltage terminal to the second output node;
• and
• a reset circuit configured to drive the first output node to the second power voltage based on the second reset signal.