Method for aliasing reduction in auto zero amplifier
AssigneeAnalog Devices International Unlimited Company
InventorsHai Chen, Gregory J. Hughes
Life of this patent
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Abstract
An electronic circuit comprises a primary amplifier circuit including a differential input and an output, an offset nulling amplifier circuit, and an impedance matching circuit. The offset nulling amplifier circuit includes a differential input and an output. The differential input of the primary amplifier circuit is operatively coupled to a differential input of the offset nulling amplifier circuit and the impedance matching circuit. The output of the offset nulling amplifier circuit is operatively coupled to the primary amplifier circuit and provides a voltage to reduce offset in an output signal of the primary amplifier circuit.
Claims20
An electronic circuit comprising:
- a primary amplifier circuit including a differential input and an output;
- an offset nulling amplifier circuit, wherein the offset nulling amplifier circuit includes a differential input and an output;
- and
- an impedance matching circuit, wherein the differential input of the primary amplifier circuit is operatively coupled to a differential input of the offset nulling amplifier circuit and the impedance matching circuit;
- wherein the output of the offset nulling amplifier circuit is operatively coupled to the primary amplifier circuit and provides a voltage to reduce offset in an output signal of the primary amplifier circuit.
A method of operating an amplifier circuit, the method comprising:
- applying an input signal to a primary amplifier circuit;
- applying the input signal to an input of an offset nulling amplifier circuit and an input of an impedance matching circuit;
- and
- using an output of the offset nulling amplifier circuit to reduce an offset voltage in an output signal of the primary amplifier circuit.
An auto-zero amplifier circuit comprising:
- a primary amplifier circuit including a differential input configured to receive a differential input signal;
- a sample and hold circuit;
- an offset nulling amplifier circuit including a differential input and an output, the differential input and the output connected to the sample and hold circuit;
- and
- a replicate circuit of a portion of the offset nulling amplifier circuit, the replicate circuit connected to the sample and hold circuit;
- wherein the sample and hold circuit is configured to sample an input offset voltage of the offset nulling amplifier circuit and reduce an offset of the primary amplifier circuit using the sampled offset voltage.
Dependencies are inferred from the claim text.