Power transistor control signal gating

A power circuit, comprising:

• a first power switch comprising:
• a first drain terminal,
• a first source terminal, and
• a first gate terminal,
• wherein a first current path between the first drain terminal and the first source terminal of the first power switch is configured to be selectively conductive according to a plurality of first gate signals at the first gate terminal;
• a first slew detect circuit configured to generate a first control signal in response to a first voltage at one of the first source and first drain terminals changing at a rate greater than a threshold rate;
• and
• a first power switch driver, configured to control a conductivity of the first current path between the first drain terminal and the first source terminal of the first power switch by generating the first gate signals at the first gate terminal of the first power switch, wherein the first power switch driver is configured to generate the first gate signals based on a received plurality of first input signals and on the first control signal, wherein the first power switch driver comprises:
• an input configured to receive the first input signals,
• an output configured to provide the first gate signals, wherein each provided first gate signal corresponds with one of the first input signals, and
• a timing control circuit, configured to, in response to the first control signal indicating that the first voltage at one of the first source and first drain terminals is changing at the rate greater than the threshold rate, conditionally generating a particular first gate signal of the first gate signals, thereby causing the first power switch to be non-conductive,
• wherein the first control signal causes the first power switch driver to delay a completion of a transition of the particular first gate signal.