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US 10,833,584 B2Granted
Boot-strapping systems and techniques for circuits
AssigneeEmpower Semiconductor, Inc.
InventorsParag Oak, Timothy A. Phillips
Life of this patent
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Abstract
Boot-strapping systems and techniques for circuits are described. One or more solid-state switches of a switched regulation circuit may be implemented using core transistors and the boot-strapping systems, rather than I/O transistors.
Claims7
A solid-state switch having first and second switch terminals and a control terminal, the solid-state switch comprising:
- first, second, third, and fourth core transistors;
- and
- a circuit component having a control terminal coupled to the control terminal of the solid-state switch,
- wherein a first diffusion terminal of the first core transistor is coupled to a first diffusion terminal of the second core transistor,
- wherein a first diffusion terminal of the third core transistor is coupled to a first diffusion terminal of the fourth core transistor, and is coupled to a gate terminal of the first core transistor via a first conductive path consisting of one or more non-parasitic circuit components,
- wherein a second diffusion terminal of the fourth core transistor is coupled to a gate terminal of the second core transistor via a second conductive path consisting of one or more non-parasitic circuit components,
- wherein a second diffusion terminal of the first core transistor is coupled to a second diffusion terminal of the third core transistor and to the first switch terminal of the solid-state switch,
- wherein a second diffusion terminal of the second core transistor is coupled to the second switch terminal of the solid-state switch, and
- wherein the circuit component is configured to selectively switch gate terminals of the third and fourth core transistors between a first configuration in which said gate terminals of the third and fourth core transistors are coupled to the first switch terminal via a third conductive path consisting of one or more non-parasitic circuit components and a second configuration in which said gate terminals of the third and fourth core transistors are coupled to a supply terminal via a fourth conductive path consisting of one or more non-parasitic circuit components.
6 more elements
Dependencies are inferred from the claim text.